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产品型号NDS9410AF011的Datasheet PDF文件预览

April 2000  
NDS9410A  
Single N-Channel Enhancement Mode Field Effect Transistor  
General Description  
Features  
This N-Channel Logic Level MOSFET is produced  
·
·
·
7.3 A, 30 V.  
RDS(ON) = 28 mW @ VGS = 10 V  
RDS(ON) = 42 mW @ VGS = 4.5 V  
using  
Fairchild  
Semiconductor’s  
advanced  
PowerTrench process that has been especially tailored  
to minimize the on-state resistance and yet maintain  
superior switching performance.  
High performance trench technology for extremely  
low RDS(ON)  
These devices are particularly suited for low voltage  
applications such as notebook computer power  
management and other battery powered circuits where  
fast switching, low in-line power loss and resistance to  
transients are needed.  
High power and current handling capability in a  
widely used surface mount package.  
D
D
D
5
6
7
8
4
3
2
1
D
G
S
S
SO-8  
S
Absolute Maximum Ratings TA=25oC unless otherwise noted  
Symbol  
VDSS  
Parameter  
Drain-Source Voltage  
Ratings  
Units  
30  
V
V
A
VGSS  
Gate-Source Voltage  
±20  
7.3  
20  
ID  
Drain Current – Continuous  
– Pulsed  
(Note 1a)  
Power Dissipation for Single Operation  
(Note 1a)  
(Note 1b)  
2.5  
1.2  
PD  
W
(Note 1c)  
1.0  
TJ, TSTG  
Operating and Storage Junction Temperature Range  
-55 to +150  
°C  
Thermal Characteristics  
Thermal Resistance, Junction-to-Ambient  
(Note 1a)  
(Note 1)  
50  
25  
RqJA  
°C/W  
°C/W  
Thermal Resistance, Junction-to-Case  
RqJC  
Package Marking and Ordering Information  
Device Marking  
Device  
Reel Size  
Tape width  
Quantity  
NDS9410A  
NDS9410A  
13’’  
12mm  
2500 units  
NDS9410A Rev B(W)  
Ó 2000 Fairchild Semiconductor Corporation  
Electrical Characteristics  
T
= 25°C unless otherwise noted  
A
Symbol  
Parameter  
Test Conditions  
Min Typ Max Units  
Off Characteristics  
BVDSS  
Drain–Source Breakdown Voltage  
30  
V
VGS = 0 V, ID = 250 mA  
DBVDSS  
DTJ  
Breakdown Voltage Temperature  
Coefficient  
ID = 250 mA, Referenced to 25°C  
28  
mV/°C  
IDSS  
Zero Gate Voltage Drain Current  
Gate–Body Leakage, Forward  
Gate–Body Leakage, Reverse  
VDS = 24 V, VGS = 0 V  
VGS = 20 V, VDS = 0 V  
VGS = –20 V VDS = 0 V  
2
mA  
nA  
nA  
IGSSF  
IGSSR  
100  
–100  
On Characteristics  
(Note 2)  
VGS(th)  
Gate Threshold Voltage  
1
1.6  
3
V
VDS = VGS, ID = 250 mA  
DVGS(th)  
DTJ  
RDS(on)  
Gate Threshold Voltage  
Temperature Coefficient  
ID = 250 mA, Referenced to 25°C  
-4.3  
mV/°C  
mW  
Static Drain–Source  
On–Resistance  
VGS = 10 V, ID = 7.3 A  
VGS = 10 V, ID = 7.3 A, TJ=125°C  
VGS = 4.5 V, ID = 6.3 A  
VGS = 4.5 V, ID = 6.3 A, TJ=125°C  
VGS = 10 V, VDS = 5 V  
19  
30  
25  
42  
28  
45  
42  
75  
ID(on)  
gFS  
On–State Drain Current  
20  
A
S
Forward Transconductance  
VDS = 15 V,  
ID = 7.3 A  
22  
Dynamic Characteristics  
Ciss  
Coss  
Crss  
Input Capacitance  
830  
185  
80  
pF  
pF  
pF  
VDS = 15 V, V GS = 0 V,  
f = 1.0 MHz  
Output Capacitance  
Reverse Transfer Capacitance  
Switching Characteristics (Note 2)  
VDD = 25 V, ID = 1 A,  
VGS = 10 V, RGEN = 6 W  
td(on)  
tr  
td(off)  
tf  
Turn–On Delay Time  
Turn–On Rise Time  
Turn–Off Delay Time  
Turn–Off Fall Time  
Total Gate Charge  
Gate–Source Charge  
Gate–Drain Charge  
6
12  
20  
32  
10  
22  
ns  
ns  
10  
18  
5
ns  
ns  
VDS = 15 V, ID = 2 A,  
VGS = 10 V  
Qg  
Qgs  
Qgd  
14  
2.7  
3.0  
nC  
nC  
nC  
Drain–Source Diode Characteristics and Maximum Ratings  
IS  
Maximum Continuous Drain–Source Diode Forward Current  
2.2  
1.1  
A
V
Drain–Source Diode Forward  
VGS = 0 V, IS = 2.2 A  
Voltage  
VSD  
(Note 2)  
0.78  
Notes:  
1. R is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of  
qJA  
the drain pins. R  
is guaranteed by design while R  
is determined by the user's board design.  
qJC  
qCA  
a) 50°/W when  
b) 105°/W when  
mounted on a .04 in2  
pad of 2 oz copper  
c) 125°/W when mounted on a  
minimum pad.  
mounted on a 1in2  
pad of 2 oz copper  
Scale 1 : 1 on letter size paper  
2. Pulse Test: Pulse Width < 300ms, Duty Cycle < 2.0%  
NDS9410A Rev B(W)  
Typical Characteristics  
30  
2.5  
2
4.0V  
VGS = 10V  
25  
VGS = 3.0V  
3.5V  
3.5V  
6.0V  
20  
15  
10  
5
5.0V  
4.5V  
3.0V  
1.5  
1
4.0V  
4.5V  
5.0V  
6.0V  
10V  
20  
2.5V  
0
0.5  
0
0.5  
1
1.5  
2
2.5  
0
5
10  
15  
25  
30  
VDS, DRAIN-SOURCE VOLTAGE (V)  
ID, DRAIN CURRENT (A)  
Figure 1. On-Region Characteristics.  
Figure 2. On-Resistance Variation with  
Drain Current and Gate Voltage.  
0.1  
0.08  
0.06  
0.04  
0.02  
0
1.8  
1.6  
1.4  
1.2  
1
D
I
= 7.3 A  
ID = 7.3A  
VGS = 10V  
TA = 125oC  
0.8  
0.6  
0.4  
TA = 25oC  
-50  
-25  
0
25  
50  
75  
100  
125  
150  
2
4
6
8
10  
TJ, JUNCTION TEMPERATURE (oC)  
VGS, GATE TO SOURCE VOLTAGE (V)  
Figure 3. On-Resistance Variation with  
Temperature.  
Figure 4. On-Resistance Variation with  
Gate-to-Source Voltage.  
100  
10  
30  
o
A
T
= -55 C  
VGS = 0V  
25
o
C  
125
o
C  
VDS = 5V  
TA = 125oC  
25  
20  
15  
10  
5
1
25o  
0.1  
o
-55 C  
0.01  
0.001  
0.0001  
0
0
0.2  
0.4  
0.6  
0.8  
1
1.2  
1.4  
0.5  
1.5  
2.5  
3.5  
4.5  
VSD, BODY DIODE FORWARD VOLTAGE (V)  
VGS, GATE TO SOURCE VOLTAGE (V)  
Figure 5. Transfer Characteristics.  
Figure 6. Body Diode Forward Voltage Variation  
with Source Current and Temperature.  
NDS9410A Rev B(W)  
Typical Characteristics  
10  
1500  
1200  
900  
600  
300  
0
f = 1MHz  
VGS = 0 V  
D
DS  
V = 5V  
I
= 7.3A  
10V  
8
6
4
2
0
15V  
CISS  
COSS  
CRSS  
0
3
6
9
12  
15  
0
5
10  
15  
20  
25  
30  
Qg, GATE CHARGE (nC)  
VDS, DRAIN TO SOURCE VOLTAGE (V)  
Figure 7. Gate Charge Characteristics.  
Figure 8. Capacitance Characteristics.  
100  
50  
40  
30  
20  
10  
0
RDS(ON) LIMIT  
m
SINGLE PULSE  
100  
s
o
1ms  
10ms  
100ms  
1s  
qJA  
R
= 125 C/W  
10  
1
o
A
T
= 25 C  
10s  
DC  
0.1  
GS  
V
= 10V  
SINGLE PULSE  
o
0.01  
q
R
JA = 125 C/W  
TA = 25oC  
0.001  
0.1  
1
10  
100  
0.001  
0.01  
0.1  
1
10  
100  
VDS, DRAIN-SOURCE VOLTAGE (V)  
t1, TIME (SEC)  
Figure 9. Maximum Safe Operating Area.  
Figure 10. Single Pulse Maximum  
Power Dissipation.  
1
D = 0.5  
q
q
R
JA(t) = r(t) + R JA  
0.2  
q
R JA = 125 °C/W  
0.1  
0.05  
0.02  
0.01  
SINGLE PULSE  
0.1  
0.01  
P(pk)  
t1  
t2  
q
JA  
J
A
T - T = P * R (t)  
Duty Cycle, D = t1 / t2  
0.001  
0.0001  
0.001  
0.01  
0.1  
1
10  
100  
1000  
t1, TIME (sec)  
Figure 11. Transient Thermal Response Curve.  
Thermal characterization performed using the conditions described in Note 1c.  
Transient thermal response will change depending on the circuit board design.  
NDS9410A Rev B(W)  
SO-8 Tape and Reel Data and Package Dimensions  
SOIC(8lds) Packaging  
Configuration: Figure 1.0  
Packaging Description:  
SOIC-8 parts are shipped in tape. The carrier tape is  
ELECTROSTATIC  
SENSITIVE DEVICES  
DO NO  
ELECTRO  
T
SHI  
P
OR STO  
RE  
N
E
AR STRO NG ELECTROS  
T
FI  
ATIC  
ELD S  
made from dissipative (carbon filled) polycarbonate  
a
M
AGN  
E
TI  
C,  
M
AG NETIC  
O
R
R
ADIO ACTIVE  
TNR DATE  
PT NUMB E  
resin. The cover tape is a multilayer film (Heat Activated  
Adhesive in nature) primarily composed of polyester film,  
adhesive layer, sealant, and anti-static sprayed agent.  
These reeled parts in standard option are shipped with  
2,500 units per 13" or 330cm diameter reel. The reels are  
dark blue in color and is made of polystyrene plastic (anti-  
static coated). Other option comes in 500 units per 7" or  
177cm diameter reel. This and some other options are  
further described in the Packaging Information table.  
R
PEEL STRENGTH MIN ______________gms  
MAX _____________gms  
Antistatic Cover Tape  
ESD Label  
These full reels are individually barcode labeled and  
placed inside  
a standard intermediate box (illustrated in  
figure 1.0) made of recyclable corrugated brown paper.  
One box contains two reels maximum. And these boxes  
are placed inside  
comes in different sizes depending on the number of parts  
shipped.  
a barcode labeled shipping box which  
Static Dissipative  
Embossed Carrier Tape  
F63TNR  
Label  
F
NDS  
9959  
852  
Customized  
Label  
F
F
F
F
Pin 1  
SOIC (8lds) Packaging Information  
Standard  
L86Z  
F011  
D84Z  
Packaging Option  
(no flow code)  
SOIC-8 Unit Orientation  
Packaging type  
TNR  
2,500  
Rail/Tube  
TNR  
4,000  
TNR  
500  
Qty per Reel/Tube/Bag  
Reel Size  
95  
-
13" Dia  
13" Dia  
7" Dia  
Box Dimension (mm)  
Max qty per Box  
343x64x343 530x130x83 343x64x343 184x187x47  
5,000  
0.0774  
0.6060  
30,000  
0.0774  
-
8,000  
0.0774  
0.9696  
1,000  
0.0774  
0.1182  
Weight per unit (gm)  
Weight per Reel (kg)  
Note/Comments  
343mm x 342mm x 64mm  
Standard Intermediate box  
ESD Label  
F63TNR Label sample  
F63TNLabel  
ESD Label  
F63TN Label  
LOT: CBVK741B019  
FSID: FDS9953A  
QTY: 2500  
SPEC:  
D/C1: D9842  
D/C2:  
QTY1:  
QTY2:  
SPEC REV:  
CPN:  
N/F: F  
(F63TNR)3  
SOIC(8lds) Tape Leader and Trailer  
Configuration: Figure 2.0  
Carrier Tape  
Cover Tape  
Components  
Trailer Tape  
Leader Tape  
640mm minimum or  
80 empty pockets  
1680mm minimum or  
210 empty pockets  
July 1999, Rev. B  
SO-8 Tape and Reel Data and Package Dimensions, continued  
SOIC(8lds) Embossed Carrier Tape  
Configuration: Figure 3.0  
P0  
D0  
T
E1  
E2  
F
W
K0  
Wc  
B0  
Tc  
A0  
D1  
P1  
User Direction of Feed  
Dimensions are in millimeter  
A0  
B0  
W
D0  
D1  
E1  
E2  
F
P1  
P0  
K0  
T
Wc  
Tc  
Pkg type  
0.450  
+/-  
0.150  
(8lds)  
SOIC  
(12mm)  
6.50  
+/-0.10  
5.30  
+/-0.10  
12.0  
+/-0.3  
1.55  
+/-0.05  
1.60  
+/-0.10  
1.75  
+/-0.10  
10.25  
min  
5.50  
+/-0.05  
8.0  
+/-0.1  
4.0  
+/-0.1  
2.1  
+/-0.10  
9.2  
+/-0.3  
0.06  
+/-0.02  
Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481  
rotational and lateral movement requirements (see sketches A, B, and C).  
0.5mm  
maximum  
20 deg maximum  
Typical  
component  
cavity  
center line  
0.5mm  
maximum  
B0  
20 deg maximum component rotation  
Typical  
component  
center line  
Sketch A (Side or Front Sectional View)  
Component Rotation  
Sketch C (Top View)  
Component lateral movement  
A0  
Sketch B (Top View)  
Component Rotation  
SOIC(8lds) Reel Configuration: Figure 4.0  
W1 Measured at Hub  
Dim A  
Max  
Dim A  
max  
See detail AA  
Dim N  
7"Diameter Option  
B Min  
Dim C  
See detail AA  
Dim D  
min  
W3  
13" Diameter Option  
W2 max Measured at Hub  
DETAIL AA  
Dim W2  
Dimensions are in inches and millimeters  
Reel  
Option  
Tape Size  
12mm  
Dim A  
Dim B  
Dim C  
Dim D  
Dim N  
Dim W1  
Dim W3 (LSL-USL)  
7.00  
177.8  
0.059  
1.5  
512 +0.020/-0.008  
13 +0.5/-0.2  
0.795  
20.2  
2.165  
55  
0.488 +0.078/-0.000  
12.4 +2/0  
0.724  
18.4  
0.469 – 0.606  
11.9 – 15.4  
7" Dia  
13.00  
330  
0.059  
1.5  
512 +0.020/-0.008  
13 +0.5/-0.2  
0.795  
20.2  
7.00  
178  
0.488 +0.078/-0.000  
12.4 +2/0  
0.724  
18.4  
0.469 – 0.606  
11.9 – 15.4  
12mm  
13" Dia  
July 1999, Rev. B  
SO-8 Tape and Reel Data and Package Dimensions, continued  
SOIC-8 (FS PKG Code S1)  
1 : 1  
Scale 1:1 on letter size paper  
Dimensions shown below are in:  
inches [millimeters]  
Part Weight per unit (gram): 0.0774  
9
September 1998, Rev. A  
TRADEMARKS  
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is  
not intended to be an exhaustive list of all such trademarks.  
ACEx™  
HiSeC™  
SuperSOT™-8  
SyncFET™  
TinyLogic™  
UHC™  
Bottomless™  
CoolFET™  
CROSSVOLT™  
E2CMOSTM  
FACT™  
ISOPLANAR™  
MICROWIRE™  
POP™  
PowerTrench  
QFET™  
VCX™  
QS™  
FACT Quiet Series™  
FAST  
FASTr™  
Quiet Series™  
SuperSOT™-3  
SuperSOT™-6  
GTO™  
DISCLAIMER  
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER  
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD  
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT  
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT  
RIGHTS, NOR THE RIGHTS OF OTHERS.  
LIFE SUPPORT POLICY  
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT  
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.  
As used herein:  
1. Life support devices or systems are devices or  
systems which, (a) are intended for surgical implant into  
the body, or (b) support or sustain life, or (c) whose  
failure to perform when properly used in accordance  
with instructions for use provided in the labeling, can be  
reasonably expected to result in significant injury to the  
user.  
2. A critical component is any component of a life  
support device or system whose failure to perform can  
be reasonably expected to cause the failure of the life  
support device or system, or to affect its safety or  
effectiveness.  
PRODUCT STATUS DEFINITIONS  
Definition of Terms  
Datasheet Identification  
Product Status  
Definition  
Advance Information  
Formative or  
In Design  
This datasheet contains the design specifications for  
product development. Specifications may change in  
any manner without notice.  
Preliminary  
First Production  
This datasheet contains preliminary data, and  
supplementary data will be published at a later date.  
Fairchild Semiconductor reserves the right to make  
changes at any time without notice in order to improve  
design.  
No Identification Needed  
Obsolete  
Full Production  
This datasheet contains final specifications. Fairchild  
Semiconductor reserves the right to make changes at  
any time without notice in order to improve design.  
Not In Production  
This datasheet contains specifications on a product  
that has been discontinued by Fairchild semiconductor.  
The datasheet is printed for reference information only.  
Rev. E  
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