PCM1794E各脚功能电路原理芯片引脚定义引脚图及功能IC贸易商-中国IC网-芯三七

PCM1795

www.ti.com ........................................................................................................................................................................................................ SLES248–MAY 2009

32-Bit, 192-kHz Sampling, Advanced Segment,

Stereo Audio Digital-to-Analog Converter

1

FEATURES

APPLICATIONS

•

A/V Receivers

SACD Players

DVD Players

HDTV Receivers

Car Audio Systems

Digital Multitrack Recorders

Other Applications Requiring 32-Bit Audio

234567

• 32-Bit Resolution

•

Analog Performance:

–

Dynamic Range: 123 dB

THD+N: 0.0005%

•

Differential Current Output: 3.9 mA_PP

8× Oversampling Digital Filter:

–

Stop Band Attenuation: –98 dB

Passband Ripple: ±0.0002 dB

DESCRIPTION

•

Sampling Frequency: 10 kHz to 200 kHz

The PCM1795 is a monolithic CMOS integrated

circuit

System Clock: 128, 192, 256, 384, 512, or

768 f_SWith Autodetect

that

includes

stereo

digital-to-analog

converters (DACs) and support circuitry in a small

SSOP-28 package. The data converters use TI’s

advanced segment DAC architecture to achieve

excellent dynamic performance and improved

tolerance to clock jitter. The PCM1795 provides

balanced current outputs, allowing the user to

optimize analog performance externally. The

PCM1795 accepts pulse code modulation (PCM) and

direct stream digital (DSD) audio data formats,

providing an easy interface to audio digital signal

processors (DSPs) and decoder chips. The PCM1795

also interfaces with external digital filter devices such

as the DF1704, DF1706, and the PMD200 from

Pacific Microsonics™. Sampling rates up to 200 kHz

are supported. A full set of user-programmable

functions is accessible through an SPI or I²C serial

control port that supports register write and readback

functions. The PCM1795 also supports the

time-division-multiplexed (TDM) command and audio

(TDMCA) data format.

•

Accepts 16-, 24-, and 32-Bit Audio Data

PCM Data Formats: Standard, I²S™, and

Left-Justified

•

DSD Format Interface Available

Interface Available for Optional External Digital

Filter or DSP

TDMCA or Serial Port (SPI™/I²C™)

•

User-Programmable Mode Controls:

–

Digital Attenuation: 0 dB to –120 dB,

0.5-dB/Step

–

Digital De-Emphasis

Digital Filter Roll-Off: Sharp or Slow

Soft Mute

Zero Flag for Each Output

•

Compatible With PCM1792A and PCM1796

(Pins and Mode Controls)

Dual Supply Operation:

–

5-V Analog, 3.3-V Digital

•

5-V Tolerant Digital Inputs

Small SSOP-28 Package

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

3

4

5

6

7

System Two, Audio Precision are trademarks of Audio Precision, Inc.

SPI is a trademark of Motorola.

I2S, I2C are trademarks of NXP Semiconductors.

Pacific Microsonics is a trademark of Pacific Microsonics, Inc.

Super Audio CD is a trademark of Sony Corporation.

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

PCM1795

SLES248–MAY 2009........................................................................................................................................................................................................ www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION⁽¹⁾

SPECIFIED

PACKAGE-

LEAD

PACKAGE

DESIGNATOR

TEMPERATURE

RANGE

PACKAGE

MARKING

ORDERING

NUMBER

TRANSPORT MEDIA,

QUANTITY

PRODUCT

PCM1795DB

Tube

PCM1795

SSOP-28

DB

–25°C to +85°C

PCM1795

PCM1795DBR

Tape and Reel

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

Over operating free-air temperature range, unless otherwise noted.

VALUE

–0.3 to +6.5

–0.3 to +4

±0.1

UNIT

V_CC1, V_CC2L, V_CC2R

V

Supply voltage

V_DD

Supply voltage differences

Ground voltage differences

V_CC1, V_CC2L, V_CC2R

AGND1, AGND2, AGND3L, AGND3R, DGND

±0.1

LRCK, DATA, BCK, SCK, MSEL, RST, MS⁽²⁾, MDI, MC,

–0.3 to +6.5

V

MDO⁽²⁾, ZEROL⁽²⁾, ZEROR⁽²⁾

Digital input voltage

ZEROL⁽³⁾, ZEROR⁽³⁾, MDO⁽³⁾, MS⁽³⁾

–0.3 to (V_DD+ 0.3) < 4

V

Analog input voltage

–0.3 to (V_CC+ 0.3) < 6.5

Input current (any pins except supplies)

Ambient temperature under bias

Storage temperature

±10

–40 to +125

–55 to +150

+150

mA

°C

Junction temperature

Package temperature (IR reflow, peak)

+260

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Input mode or I²C mode.

(3) Output mode except for I²C mode.

2

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www.ti.com ........................................................................................................................................................................................................ SLES248–MAY 2009

ELECTRICAL CHARACTERISTICS

All specifications at T_A= +25°C, V_CC1 = V_CC2L = V_CC2R = 5 V, V_DD= 3.3 V, f_S= 48 kHz, system clock = 256 f_S, and 32-bit

data, unless otherwise noted.

PCM1795 DB

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

RESOLUTION

Resolution

DATA FORMAT (PCM Mode)

Audio data interface format

32

Bits

Standard, I²S, left-justified

16-, 24-, 32-bit selectable

Audio data bit length

Audio data format

MSB first, twos complement

10

f_S

Sampling frequency

System clock frequency

200

kHz

f_S

128, 192, 256, 384, 512, 768

DATA FORMAT (DSD Mode)

Audio data interface format

DSD (direct stream digital)

Audio data bit length

Sampling frequency

System clock frequency

1

Bit

f_S

2.8224

MHz

2.8224

11.2986

DIGITAL INPUT/OUTPUT

TTL

compatible

Logic family

V_IH

2

VDC

µA

Input logic level

V_IL

0.8

10

I_IH

V_IN= V_DD

V_IN= 0 V

Input logic current

I_IL

–10

µA

V_OH

I_OH= –2 mA

I_OL= 2 mA

2.4

VDC

Output logic level

V_OL

0.4

DYNAMIC PERFORMANCE (PCM MODE)⁽¹⁾⁽²⁾

f_S= 48 kHz

f_S= 96 kHz

0.0005

0.001

0.0015

123

0.001

%

THD+N at V_OUT= 0 dB

%

f_S= 192 kHz

%

EIAJ, A-weighted, f_S= 48 kHz

EIAJ, A-weighted, f_S= 96 kHz

EIAJ, A-weighted, f_S= 192 kHz

EIAJ, A-weighted, f_S= 48 kHz

EIAJ, A-weighted, f_S= 96 kHz

EIAJ, A-weighted, f_S= 192 kHz

f_S= 48 kHz

120

116

dB

Dynamic range

123

Signal-to-noise ratio

Channel separation

123

119

f_S= 96 kHz

118

f_S= 192 kHz

117

Level linearity error

(1) Filter condition:

V_OUT= –120 dB

±1

THD+N: 20-Hz high-pass filter (HPF), 20-kHz AES17 low-pass filter (LPF)

Dynamic range: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted

Signal-to-noise ratio: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted

Channel separation: 20-Hz HPF, 20-kHz AES17 LPF

Analog performance specifications are measured using the System Two™ Cascade audio measurement system by Audio Precision™ in

the averaging mode.

(2) Dynamic performance and dc accuracy are specified at the output of the post-amplifier as shown in Figure 52.

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ELECTRICAL CHARACTERISTICS (continued)

All specifications at T_A= +25°C, V_CC1 = V_CC2L = V_CC2R = 5 V, V_DD= 3.3 V, f_S= 48 kHz, system clock = 256 f_S, and 32-bit

data, unless otherwise noted.

PCM1795 DB

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DYNAMIC PERFORMANCE (MONO MODE)^(3)(4)(5)

f_S= 48 kHz

0.0005

0.001

0.0015

126

%

THD+N at V_OUT= 0 dB

Dynamic range

f_S= 96 kHz

f_S= 192 kHz

%

EIAJ, A-weighted, f_S= 48 kHz

EIAJ, A-weighted, f_S= 96 kHz

EIAJ, A-weighted, f_S= 192 kHz

EIAJ, A-weighted, f_S= 48 kHz

EIAJ, A-weighted, f_S= 96 kHz

EIAJ, A-weighted, f_S= 192 kHz

dB

126

Signal-to-noise ratio

126

DSD MODE DYNAMIC PERFORMANCE (44.1 kHz, 64 f_S)⁽³⁾⁽⁶⁾

THD+N at FS

2 V rms

0.0007

122

%

Dynamic range

–60 dB, EIAJ, A-weighted

EIAJ, A-weighted

dB

Signal-to-noise ratio

122

ANALOG OUTPUT

Gain error

–7

–3

–2

±2

±0.5

4

7

3

2

% of FSR

mA_PP

Gain mismatch, channel-to-channel

Bipolar zero error

Output current

At BPZ

Full-scale (0 dB)

At BPZ

Center current

–3.5

mA

DIGITAL FILTER PERFORMANCE

De-emphasis error

±0.1

dB

FILTER CHARACTERISTICS–1: SHARP ROLL-OFF

±0.0002 dB

–3 dB

0.454

0.49

f_S

Passband

Stop band

Passband ripple

0.546

–98

f_S

±0.0002

dB

s

Stop-band attenuation

Stop band = 0.546 f_S

Delay time

38/f_S

FILTER CHARACTERISTICS–2: SLOW ROLL-OFF

±0.001 dB

–3 dB

0.21

f_S

Passband

0.448

Stop band

0.79

–80

f_S

Passband ripple

Stop-band attenuation

Delay time

±0.001

dB

s

Stop band = 0.732 f_S

38/f_S

(3) Filter condition:

THD+N: 20-Hz high-pass filter (HPF), 20-kHz AES17 low-pass filter (LPF)

Dynamic range: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted

Signal-to-noise ratio: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted

Channel separation: 20-Hz HPF, 20-kHz AES17 LPF

Analog performance specifications are measured using the System Two™ Cascade audio measurement system by Audio Precision™ in

the averaging mode.

(4) Dynamic performance and dc accuracy are specified at the output of the post-amplifier as shown in Figure 52.

(5) Dynamic performance and dc accuracy are specified at the output of the measurement circuit as shown in Figure 54.

(6) Dynamic performance and dc accuracy are specified at the output of the post-amplifier as shown in Figure 53.

4

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www.ti.com ........................................................................................................................................................................................................ SLES248–MAY 2009

ELECTRICAL CHARACTERISTICS (continued)

All specifications at T_A= +25°C, V_CC1 = V_CC2L = V_CC2R = 5 V, V_DD= 3.3 V, f_S= 48 kHz, system clock = 256 f_S, and 32-bit

data, unless otherwise noted.

PCM1795 DB

PARAMETER

POWER-SUPPLY REQUIREMENTS

V_DD

TEST CONDITIONS

MIN

3

TYP

3.3

5

MAX

3.6

5.25

8

UNIT

VDC

V_CC

1

Voltage range

V_CC2L

V_CC2R

4.75

f_S= 48 kHz

f_S= 96 kHz

f_S= 192 kHz

f_S= 44.1 kHz

f_S= 96 kHz

f_S= 192 kHz

f_S= 48 kHz

f_S= 96 kHz

f_S= 192 kHz

6

11

mA

mW

I_DD

21

Supply current⁽⁷⁾

18

23

I_CC

19

20

110

131

166

141

Power dissipation⁽⁷⁾

TEMPERATURE RANGE

Operating temperature

Thermal resistance

–25

+85

°C

θ_JA

SSOP-28

+100

°C/W

(7) Input is bipolar zero (BPZ) data.

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PCM1795

SLES248–MAY 2009........................................................................................................................................................................................................ www.ti.com

FUNCTIONAL BLOCK DIAGRAM

I_OUTL-

LRCK

Current

Segment

DAC

V_OUTL

BCK

Audio

Data Input

I/F

DATA

I_OUTL+

I/V and Filter

RST

V_COM

L

x8

Advanced

Segment

DAC

Oversampling

Digital Filter

and

I_REF

Bias

and V_REF

V_COM

R

Modulator

MDO

MDI

MC

Function Control

I_OUTR-

Function

Control I/F

MS

Current

Segment

DAC

V_OUTR

I_OUTR+

MSEL

I/V and Filter

System

Clock

Manager

ZEROL

ZEROR

Zero

Detect

Power Supply

6

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www.ti.com ........................................................................................................................................................................................................ SLES248–MAY 2009

PIN CONFIGURATION

DB PACKAGE

SSOP-28

(TOP VIEW)

V_CC2L

27 AGND3L

ZEROL

ZEROR

MSEL

LRCK

DATA

BCK

1

2

28

I_OUTL-

I_OUTL+

AGND2

3

26

25

24

23

22

21

20

4

5

V_CC1

6

V_COM

I_REF

L

SCL

7

R

DGND

V_DD

8

9

10

19 AGND1

MS

I_OUTR-

MDI 11

MC 12

18

17

I_OUTR+

MDO 13

16 AGND3R

V_CC2R

15

14

RST

Table 1. TERMINAL FUNCTIONS

TERMINAL

NAME

AGND1

AGND2

AGND3L

AGND3R

BCK

NO.

19

24

27

16

6

I/O

—

I

DESCRIPTION

Analog ground (internal bias)

Analog ground (left channel DACFF)

Analog ground (right channel DACFF)

Bit clock input⁽¹⁾

DATA

DGND

I_OUTL+

I_OUTL–

I_OUTR+

I_OUTR–

I_REF

5

I

Serial audio data input⁽²⁾

8

—

O

—

I

Digital ground

25

26

17

18

20

4

Left channel analog current output+

Left channel analog current output–

Right channel analog current output+

Right channel analog current output–

Output current reference bias pin

Left and right clock (f_S) input⁽²⁾

Mode control clock input⁽²⁾

LRCK

MC

12

11

13

10

3

I

MDI

I

Mode control data input⁽²⁾

MDO

I/O

I/OI

I

Mode control readback data output⁽³⁾

Mode control chip-select input⁽⁴⁾; active low

I²C/SPI select⁽²⁾; active low SPI select

Reset⁽²⁾; active low

MS

MSEL

RST

14

I

(1) Schmitt-trigger input, 5-V tolerant.

(2) Schmitt-trigger input, 5-V tolerant.

(3) Schmitt-trigger input and output. 5-V tolerant input. In I²C mode, this pin becomes an open-drain 3-state output; otherwise, this pin is a

CMOS output.

(4) Schmitt-trigger input and output. 5-V tolerant input and CMOS output.

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Table 1. TERMINAL FUNCTIONS (continued)

TERMINAL

NAME

NO.

7

I/O

I

DESCRIPTION

SCK

System clock input⁽²⁾

V_CC

1

23

28

15

22

21

9

—

I/O

Analog power supply, 5 V

V_CC2L

V_CC2R

Analog power supply (left channel DACFF), 5 V

Analog power supply (right channel DACFF), 5 V

Left channel internal bias decoupling pin

Right channel internal bias decoupling pin

Digital power supply, 3.3 V

Zero flag for left channel⁽⁴⁾

Zero flag for right channel⁽⁴⁾

V_COM

V_DD

L

R

ZEROL

ZEROR

1

2

8

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www.ti.com ........................................................................................................................................................................................................ SLES248–MAY 2009

TIMING CHARACTERISTICS

Start

Repeated Start

Stop

t_(D-HD)

t_(SDA-F)

t_(P-SU)

t_(BUF)

t_(D-SU)

t_(SDA-R)

SDA

SCL

t_(SCL-R)

t_(RS-HD)

t_(SP)

t_(LOW)

t_(SCL-F)

t_(S-HD)

t_(HI)

t_(RS-SU)

Figure 1. Timing Definition on the I²C Bus

TIMING REQUIREMENTS

PARAMETER

CONDITIONS

Standard

MIN

MAX

UNIT

kHz

µs

ns

µs

ns

µs

ns

µs

ns

pF

ns

100

400

f_(SCL)

t_(BUF)

t_(LOW)

t_(HI)

SCL clock frequency

Fast

Standard

4.7

Bus free time between stop and start conditions

Low period of the SCL clock

High period of the SCL clock

Setup time for (repeated) start condition

Hold time for (repeated) start condition

Data setup time

Fast

1.3

Standard

Fast

4.7

1.3

Standard

Fast

4

600

Standard

Fast

4.7

t_(RS-SU)

600

t_(S-HD)

Standard

Fast

4

t_(RS-HD)

600

Standard

Fast

250

t_(D-SU)

100

Standard

Fast

0

900

t_(D-HD)

Data hold time

0

Standard

Fast

20 + 0.1 C_B

4

1000

300

t_(SCL-R)

t_(SCL-R1)

t_(SCL-F)

t_(SDA-R)

t_(SDA-F)

t_(P-SU)

Rise time of SCL signal

Standard

Fast

1000

300

Rise time of SCL signal after a repeated start condition

and after an acknowledge bit

Standard

Fast

1000

300

Fall time of SCL signal

Rise time of SDA signal

Fall time of SDA signal

Setup time for stop condition

Standard

Fast

1000

300

Standard

Fast

1000

300

Standard

Fast

600

C_(B)

t_(SP)

Capacitive load for SDA and SCL line

Pulse duration of suppressed spike

400

50

Fast

Noise margin at high level for each connected device

(including hysteresis)

V_NH

0.2 V_DD

V

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PCM1795

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TYPICAL CHARACTERISTICS: DIGITAL FILTER

Digital Filter Response

AMPLITUDE vs FREQUENCY

0

-20

0.0005

0.0004

0.0003

0.0002

0.0001

0

Frequency Response

Sharp Roll-Off

Passband Ripple

Sharp Roll-Off

-40

-60

-80

-0.0001

-0.0002

-0.0003

-0.0004

-0.0005

-100

-120

-140

-160

0

1

2

3

4

0

0.1

0.2

0.3

0.4

0.5

Frequency (´ f_S)

Figure 2.

Figure 3.

AMPLITUDE vs FREQUENCY

0

-20

0

-2

Frequency Response

Slow Roll-Off

-4

-40

-6

-60

-8

-80

-10

-12

-14

-16

-18

-20

-100

-120

-140

-160

Transition Characteristics

Slow Roll-Off

0

1

2

3

4

0

0.1

0.2

0.3

0.4

0.5

0.6

Frequency (´ f_S)

Figure 4.

Figure 5.

10

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TYPICAL CHARACTERISTICS: DIGITAL FILTER

De-Emphasis Filter

DE-EMPHASIS LEVEL vs FREQUENCY

DE-EMPHASIS ERROR vs FREQUENCY

0

-1

-2

-3

-4

-5

-6

-7

-8

-9

-10

0.5

0.4

f_S= 32 kHz

0.3

0.2

0.1

0

-0.1

-0.2

-0.3

-0.4

-0.5

0

2

4

6

8

10

12

14

0

2

4

6

8

10

12

14

Frequency (kHz)

Figure 6.

Figure 7.

DE-EMPHASIS LEVEL vs FREQUENCY

DE-EMPHASIS ERROR vs FREQUENCY

0

-1

-2

-3

-4

-5

-6

-7

-8

-9

-10

0.5

0.4

f_S= 44.1 kHz

0.3

0.2

0.1

0

-0.1

-0.2

-0.3

-0.4

-0.5

2

4

6

8

10

12

14

16

18

20

2

4

6

8

10

12

14

16

18

20

Frequency (kHz)

Figure 8.

Figure 9.

DE-EMPHASIS LEVEL vs FREQUENCY

DE-EMPHASIS ERROR vs FREQUENCY

0

-1

-2

-3

-4

-5

-6

-7

-8

-9

-10

0.5

0.4

f_S= 48 kHz

0.3

0.2

0.1

0

-0.1

-0.2

-0.3

-0.4

-0.5

2

4

6

8

10 12 14 16 18 20 22

2

4

6

8

10 12 14 16 18 20 22

Frequency (kHz)

Figure 10.

Figure 11.

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TYPICAL CHARACTERISTICS: ANALOG DYNAMIC PERFORMANCE

Supply Voltage Characteristics

PCM mode, T_A= +25°C, and V_DD= 3.3 V; measured with circuit shown in Figure 52, unless otherwise noted.

THD+N vs SUPPLY VOLTAGE

DYNAMIC RANGE vs SUPPLY VOLTAGE

0.01

126

124

122

120

118

116

f_S= 192 kHz

f_S= 96 kHz

f_S= 192 kHz

f_S= 96 kHz

f_S= 48 kHz

0.001

f_S= 48 kHz

0.0001

4.50

4.75

5.00

5.25

5.50

4.50

4.75

5.00

5.25

5.50

Supply Voltage (V)

Figure 12.

Figure 13.

SNR vs SUPPLY VOLTAGE

CHANNEL SEPARATION vs SUPPLY VOLTAGE

126

124

122

120

118

116

122

120

118

116

114

112

f_S= 96 kHz

f_S= 48 kHz

f_S= 96 kHz

f_S= 48 kHz

f_S= 192 kHz

4.50

4.75

5.00

5.25

5.50

4.50

4.75

5.00

5.25

5.50

Supply Voltage (V)

Figure 14.

Figure 15.

12

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TYPICAL CHARACTERISTICS: ANALOG DYNAMIC PERFORMANCE

Temperature Characteristics

PCM mode, V_DD= 3.3 V, and V_CC= 5 V; measured with circuit shown in Figure 52, unless otherwise noted.

THD+N vs FREE-AIR TEMPERATURE

DYNAMIC RANGE vs FREE-AIR TEMPERATURE

0.01

126

124

122

120

118

116

f_S= 96 kHz

f_S= 192 kHz

f_S= 48 kHz

0.001

f_S= 48 kHz

f_S= 96 kHz

0.0001

-50

-25

0

25

50

75

100

-50

-25

0

25

50

75

100

Free-Air Temperature (°C)

Figure 16.

Figure 17.

SNR vs FREE-AIR TEMPERATURE

CHANNEL SEPARATION vs FREE-AIR TEMPERATURE

126

124

122

120

118

116

122

120

118

116

114

112

f_S= 96 kHz

f_S= 48 kHz

f_S= 192 kHz

f_S= 48 kHz

-50

-25

0

25

50

75

100

-50

-25

0

25

50

75

100

Free-Air Temperature (°C)

Figure 18.

Figure 19.

AMPLITUDE vs FREQUENCY

(Measurement Circuit: Figure 52)

AMPLITUDE vs FREQUENCY

(Measurement Circuit: Figure 52)

0

-20

0

-60-dB Output Spectrum

BW = 20 kHz

PCM Mode

f_S= 48 kHz

BW = 100 kHz

PCM Mode

f_S= 96 kHz

-20

-40

32768 Point 8 Average

T_A= +25°C

32768 Point 8 Average

T_A= +25°C

-60

V_DD= 3.3 V

V_CC= 5 V

V_DD= 3.3 V

V_CC= 5 V

-80

-100

-120

-140

-160

-100

-120

-140

-160

0

2

4

6

8

10

12

14

16

18

20

0

10

20

30

40

50

60

70

80

90 100

Frequency (kHz)

Figure 20.

Figure 21.

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TYPICAL CHARACTERISTICS: ANALOG DYNAMIC PERFORMANCE (continued)

PCM mode, V_DD= 3.3 V, and V_CC= 5 V; measured with circuit shown in Figure 52, unless otherwise noted.

AMPLITUDE vs FREQUENCY

(Measurement Circuit: Figure 52)

AMPLITUDE vs FREQUENCY

(Measurement Circuit: Figure 52)

-120

-124

-128

-132

-136

-140

-144

-148

-152

-156

-160

-120

-124

-128

-132

-136

-140

-144

-148

-152

-156

-160

-144-dB Output Spectrum

-150-dB Output Spectrum

BW = 20 kHz

PCM Mode

f_S= 48 kHz

BW = 20 kHz

PCM Mode

f_S= 48 kHz

32768 Point 8 Average

T_A= +25°C

32768 Point 8 Average

T_A= +25°C

V_DD= 3.3 V

V_CC= 5 V

V_DD= 3.3 V

V_CC= 5 V

100

1 k

10 k

100

1 k

10 k

Frequency (Hz)

Figure 22.

Figure 23.

THD+N vs INPUT LEVEL

(Measurement Circuit: Figure 52)

AMPLITUDE vs FREQUENCY

(Measurement Circuit: Figure 53)

10

0

-20

PCM Mode

-60-dB Output Spectrum

f_S= 48 kHz

T_A= +25°C

V_DD= 3.3 V

V_CC= 5 V

DSD Mode (FIR-2)

32768 Point 8 Average

T_A= +25°C

1

0.1

-40

V_DD= 3.3 V

V_CC= 5 V

-60

-80

0.01

-100

-120

-140

-160

0.001

0.0001

-90 -80 -70 -60 -50 -40 -30 -20 -10

0

2

4

6

8

10

12

14

16

18

20

Input Level (dBFS)

Frequency (kHz)

Figure 24.

Figure 25.

14

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TYPICAL CHARACTERISTICS: ANALOG FIR FILTER PERFORMANCE IN DSD MODE

All specifications at DBCK = 2.8224 MHz (44.1 kHz × 64 f_S), and 50% modulation DSD data input, unless otherwise noted.

GAIN vs FREQUENCY

GAIN vs FREQUENCY⁽¹⁾

0

-1

-2

-3

-4

-5

-6

0

-10

-20

-30

-40

-50

-60

DSD Filter-1

Low Bandwidth

DSD Filter-1

High Bandwidth

f_C= 185 kHz

Gain = -6.6 dB

0

50

100

150

200

0

500 k

Frequency (Hz)

1 M

1.5 M

Frequency (kHz)

Figure 26.

Figure 27.

GAIN vs FREQUENCY

0

-1

-2

-3

-4

-5

-6

0

-10

-20

-30

-40

-50

-60

DSD Filter-2

Low Bandwidth

DSD Filter-2

High Bandwidth

f_C= 90 kHz

Gain = 0.3 dB

100

150

200

500 k

Frequency (Hz)

1 M

1.5 M

Frequency (kHz)

Figure 28.

Figure 29.

GAIN vs FREQUENCY

0

-1

-2

-3

-4

-5

-6

0

-10

-20

-30

-40

-50

-60

DSD Filter-3

Low Bandwidth

DSD Filter-3

High Bandwidth

f_C= 85 kHz

Gain = -1.5 dB

100

150

200

500 k

Frequency (Hz)

1 M

1.5 M

Frequency (kHz)

Figure 30.

Figure 31.

(1) This gain is in comparison to PCM 0 dB, when the DSD input signal efficiency is 50%.

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TYPICAL CHARACTERISTICS: ANALOG FIR FILTER PERFORMANCE IN DSD MODE (continued)

All specifications at DBCK = 2.8224 MHz (44.1 kHz × 64 f_S), and 50% modulation DSD data input, unless otherwise noted.

GAIN vs FREQUENCY

0

-1

-2

-3

-4

-5

-6

0

-10

-20

-30

-40

-50

-60

DSD Filter-4

Low Bandwidth

DSD Filter-4

High Bandwidth

f_C= 94 kHz

Gain = -3.3 dB

0

50

100

150

200

0

500 k

Frequency (Hz)

1 M

1.5 M

Frequency (kHz)

Figure 32.

Figure 33.

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GENERAL DESCRIPTION

SYSTEM CLOCK AND RESET FUNCTIONS

System Clock Input

The PCM1795 requires a system clock to operate the digital interpolation filters and advanced segment DAC

modulators. The system clock is applied at the SCK input (pin 7). The PCM1795 has a system clock detection

circuit that automatically senses the frequency at which the system clock is operating. Table 2 shows examples

of system clock frequencies for common audio sampling rates. If the oversampling rate of the delta-sigma (ΔΣ)

modulator is selected as 128 f_S, the system clock frequency is required to be greater than 256 f_S.

Figure 34 and Table 3 show the timing requirements for the system clock input. For optimal performance, it is

important to use a clock source with low phase jitter and noise. The Texas Instruments PLL1700 family of

multiclock generators is an excellent choice to provide the PCM1795 system clock.

Table 2. System Clock Rates for Common Audio Sampling Frequencies

SYSTEM CLOCK FREQUENCY (f_SCK) (MHz)

SAMPLING FREQUENCY

(kHz)

32

128 f_S

4.096⁽¹⁾

5.6488⁽¹⁾

6.144⁽¹⁾

12.288

192 f_S

6.144⁽¹⁾

8.4672

9.216

256 f_S

8.192

384 f_S

12.288

512 f_S

16.384

22.5792

24.576

49.152⁽¹⁾

X⁽²⁾

768 f_S

24.576

33.8688

36.864

73.728⁽¹⁾

X⁽²⁾

44.1

48

11.2896

12.288

24.576

49.152⁽¹⁾

16.9344

18.432

96

18.432

36.864

73.728⁽¹⁾

192

24.576

(1) This system clock rate is not supported in I²C fast mode.

(2) This system clock rate is not supported for the given sampling frequency.

t_(SCKH)

High

2 V

System Clock

(SCK)

0.8 V

Low

t_(SCKL)

t_(SCY)

Figure 34. System Clock Input Timing

Table 3. Timing Characteristics for Figure 34

PARAMETER

MIN

13

MAX

UNIT

ns

t_(SCY)

System clock pulse cycle time

System clock pulse duration, high

System clock pulse duration, low

t_(SCKH)

t_(SCKL)

0.4t_(SCY)

ns

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Power-On and External Reset Functions

The PCM1795 includes a power-on reset function, as shown in Figure 35. With V_DD> 2 V, the power-on reset

function is enabled. The initialization sequence requires 1024 system clocks from the time V_DD> 2 V. After the

initialization period, the PCM1795 is set to its default reset state, as described in the Mode Control Registers

section.

The PCM1795 also includes an external reset capability using the RST input (pin 14). This feature allows an

external controller or master reset circuit to force the PCM1795 to initialize to the default reset state.

Figure 36 and Table 4 show the external reset operation and timing. The RST pin is set to logic 0 for a minimum

of 20 ns. The RST pin is then set to a logic 1 state, thus starting the initialization sequence that requires 1024

system clock periods. The external reset is especially useful in applications where there is a delay between the

PCM1795 power-up and system clock activation.

V_DD

2.4 V (Max)

2 V (Typ)

1.6 V (Min)

Reset

Reset Removal

Internal Reset

System Clock

1024 System Clocks

Figure 35. Power-On Reset Timing

RST (Pin 14)

1.4 V

t_(RST)

Reset

Reset Removal

Internal Reset

System Clock

1024 System Clocks

Figure 36. External Reset Timing

Table 4. Timing Characteristics for Figure 36

PARAMETER

MIN

20

MAX

UNIT

t_(RST)

Reset pulse duration, low

ns

18

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AUDIO DATA INTERFACE

Audio Serial Interface

The audio interface port is a three-wire serial port. It includes LRCK (pin 4), BCK (pin 6), and DATA (pin 5). BCK

is the serial audio bit clock, and it is used to clock the serial data present on DATA into the serial shift register of

the audio interface. Serial data are clocked into the PCM1795 on the rising edge of BCK. LRCK is the serial

audio left/right word clock.

The PCM1795 requires the synchronization of LRCK and the system clock, but does not need a specific phase

relation between LRCK and the system clock.

If the relationship between LRCK and the system clock changes more than ±6 BCK, internal operation is

initialized within 1/f_Sand analog outputs are forced to the bipolar zero level until resynchronization between

LRCK and the system clock is completed.

PCM Audio Data Formats and Timing

The PCM1795 supports industry-standard audio data formats, including standard right-justified, I²S, and

left-justified. The data formats are illustrated in Figure 38 to Figure 40. Data formats are selected using the

format bits, FMT[2:0], in control register 18. The default data format is 32-bit I²S. All formats require binary twos

complement, MSB-first audio data. Figure 37 and Table 5 show a detailed timing diagram for the serial audio

interface.

1.4 V

LRCK

t_(BCH)

t_(BCL)

t_(LB)

BCK

t_(BCY)

t_(BL)

DATA

t_(DS)

t_(DH)

Figure 37. Audio Interface Timing

Table 5. Timing Characteristics for Figure 37

PARAMETER

MIN

70

30

10

MAX

UNIT

t_(BCY)

t_(BCL)

t_(BCH)

t_(BL)

BCK pulse cycle time

BCK pulse duration, low

BCK pulse duration, high

BCK rising edge to LRCK edge

LRCK edge to BCK rising edge

DATA setup time

ns

t_(LB)

t_(DS)

t_(DH)

—

DATA hold time

LRCK clock data

50% ± 2 bit clocks

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1/f_S

Right Channel

LRCK

Left Channel

BCK

Audio Data Word = 16-Bit, BCK ³ 32 f_S

14 15 16

1

2

15 16

LSB

1

2

15 16

DATA

MSB

Audio Data Word = 24-Bit, BCK ³ 48 f_S

23 24

1

2

23 24

LSB

1

2

23 24

31 32

22

DATA

MSB

Audio Data Word = 32-Bit, BCK ³ 64 f_S

30 31 32

31

1

2

32

1

2

DATA

MSB

LSB

Figure 38. Audio Data Input Format: Standard Data Format (Right-Justified), Left Channel = High, Right

Channel = Low

1/f_S

Right Channel

LRCK

Left Channel

BCK

Audio Data Word = 24-Bit, BCK ³ 48 f_S

DATA

1

2

23 24

LSB

1

2

23 24

1

2

MSB

Figure 39. Audio Data Input Format: Left-Justified Data Format, Left Channel = High, Right Channel =

Low

1/f_S

LRCK

Left Channel

Right Channel

BCK

Audio Data Word = 24-Bit, BCK ³ 48 f_S

23 24

LSB

1

2

23 24

1

2

1

2

DATA

MSB

Audio Data Word = 32-Bit, BCK ³ 64 f_S

DATA

2

31 32

LSB

31 32

MSB

Figure 40. Audio Data Input Format: I²S Data Format, Left Channel = Low, Right Channel = High

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External Digital Filter Interface and Timing

The PCM1795 supports an external digital filter interface that consists of a three- or four-wire synchronous serial

port that allows the use of an external digital filter. External filters include the Texas Instruments’ DF1704 and

DF1706, the Pacific Microsonics PMD200, or a programmable digital signal processor.

In the external DF mode, LRCK (pin 4), BCK (pin 6) and DATA (pin 5) are defined as: WDCK, the word clock;

BCK, the bit clock; and DATA, the monaural data. The external digital filter interface is selected by using the

DFTH bit of control register 20, which functions to bypass the internal digital filter of the PCM1795.

When the DFMS bit of control register 19 is set, the PCM1795 can process stereo data. In this case, ZEROL (pin

1) and ZEROR (pin 2) are defined as left-channel data and right-channel data input, respectively.

Detailed information for the external digital filter interface mode is provided in the Application For External Digital

Filter Interface section.

Direct Stream Digital (DSD) Format Interface and Timing

The PCM1795 supports the DSD format interface operation, which includes out-of-band noise filtering using an

internal analog FIR filter. For DSD operation, SCK (pin 7) is redefined as BCK, DATA (pin 5) as DATAL (left

channel audio data), and LRCK (pin 4) as DATAR (right channel audio data). BCK (pin 6) must be forced low in

the DSD mode. The DSD format interface is activated by setting the DSD bit of control register 20.

Detailed information for the DSD mode is provided in the Application For DSD Format (DSD Mode) Interface

section.

TDMCA Interface

The PCM1795 supports the time-division-multiplexed command and audio (TDMCA) data format to enable

control of and communication with a number of external devices over a single serial interface.

Detailed information for the TDMCA format is provided in the TDMCA Interface Format section.

FUNCTION DESCRIPTIONS

Zero Detect

The PCM1795 has a zero-detect function. When the PCM1795 detects the zero conditions as shown in Table 6,

the PCM1795 sets ZEROL (pin 1) and ZEROR (pin 2) high.

Table 6. Zero Conditions

MODE

PCM

DETECTING CONDITION AND TIME

DATA is continuously low for 1024 LRCKs.

External DF mode

DATA is continuously low for 1024 WDCKs.

There are an equal number of 1s and 0s in every 8 bits of DSD input data for 23

ms.

DZ0

DZ1

DSD

The input data are continuously 1001 0110 for 23 ms.

SERIAL CONTROL INTERFACE

The PCM1795 supports both SPI and I²C interfaces that set the mode control registers; see Table 9. The serial

control interface is selected by MSEL (pin 3); SPI is activated when MSEL is set low, and I²C is activated when

MSEL is set high.

SPI Interface

The SPI interface is a four-wire synchronous serial port that operates asynchronously to the serial audio interface

and the system clock (SCK). The serial control interface is used to program and read the on-chip mode registers.

The control interface includes MDO (pin 13), MDI (pin 11), MC (pin 12), and MS (pin 10). MDO is the serial data

output, used to read back the values of the mode registers; MDI is the serial data input, used to program the

mode registers; MC is the serial bit clock, used to shift data in and out of the control port; and MS is the mode

control enable, used to enable the internal mode register access.

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Register Read/Write Operation

All read/write operations for the serial control port use 16-bit data words. Figure 41 shows the control data word

format. The most significant bit (MSB) is the read/write (R/W) bit. For write operations, the R/W bit must be set to

'0'. For read operations, the R/W bit must be set to '1'. There are seven bits, labeled IDX[6:0], that hold the

register index (or address) for the read and write operations. The least significant eight bits, D[7:0], contain the

data to be written to, or the data that was read from, and the register specified by IDX[6:0].

Figure 42 shows the functional timing diagram for writing or reading the serial control port. MS is held at a logic 1

state until a register must be written to or read from. To start the register write or read cycle, MS is set to logic 0.

Sixteen clocks are then provided on MC, corresponding to the 16 bits of the control data word on MDI and

readback data on MDO. After the eighth clock cycle has completed, the data from the indexed-mode control

register appears on MDO during the read operation. After the 16th clock cycle has completed, the data are

latched into the indexed-mode control register during the write operation. To write or read subsequent data, MS

must be set to '1' once.

LSB

D0

MSB

R/W

IDX6

IDX5

IDX4

IDX3

IDX2

IDX1

IDX0

D7

D6

D5

D4

D3

D2

D1

Register Index (or Address)

Register Data

Figure 41. Control Data Word Format for MDI

MS

MC

MDI

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

R/W

High Impedance

MDO

D1

When Read Mode is Instructed

NOTE: Bit 15 is used for selection of write or read. Setting R/W = 0 indicates a write, while R/W = 1 indicates a read. Bits 14–8 are used for

the register address. Bits 7–0 are used for register data.

Figure 42. Serial Control Format

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t_(MHH)

1.4 V

MS

t_(MSS)

t_(MCH)

t_(MCL)

t_(MSH)

MC

1.4 V

t_(MCY)

LSB

MDI

t_(MDS)

t_(MOS)

t_(MDH)

50% of V_DD

MDO

Figure 43. Control Interface Timing

Timing Characteristics for Figure 43

PARAMETER

MIN

100

40

MAX

UNIT

ns

t_(MCY)

t_(MCL)

t_(MCH)

t_(MHH)

t_(MSS)

t_(MSH)

t_(MDH)

t_(MDS)

t_(MOS)

MC pulse cycle time

MC low-level time

ns

MC high-level time

MS high-level time

40

ns

80

ns

MS falling edge to MC rising edge

MS hold time⁽¹⁾

15

ns

15

ns

MDI hold time

15

ns

MDI setup time

15

ns

MC falling edge to MDO stable

30

ns

(1) MC rising edge for LSB to MS rising edge.

I²C INTERFACE

The PCM1795 supports the I²C serial bus and the data transmission protocol for standard and fast mode as a

slave device. This protocol is explained in the I²C specification 2.0.

In I²C mode, the control terminals are changed as described in Table 7.

Table 7. Control Terminals

TERMINAL NAME

TDMCA NAME

ADR0

PROPERTY

Input

DESCRIPTION

I²C address 0

I²C address 1

I²C clock

MS

MDI

MC

ADR1

Input

SCL

Input

MDO

SDA

Input/output

I²C data

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Slave Address

The PCM1795 has seven bits for its own slave address, as shown in Figure 44. The first five bits (MSBs) of the

slave address are factory preset to 10011. The next two bits of the address byte are the device select bits that

can be user-defined by the ADR1 and ADR0 terminals. A maximum of four PCM1795s can be connected on the

same bus at one time. Each PCM1795 responds when it receives its own slave address.

MSB

1

LSB

R/W

0

1

ADR1

ADR0

Figure 44. Slave Address

Packet Protocol

A master device must control packet protocol that consists of a start condition, slave address, read/write bit, data

if write or acknowledge if read, and stop condition. The PCM1795 supports only slave receivers and slave

transmitters.

SDA

SCL

St

17

8

9

18

9

18

9

Sp

Slave Address

R/W

ACK

DATA

ACK

DATA

ACK

R/W: Read Operation if 1; Otherwise, Write Operation

ACK: Acknowledgment of a Byte if 0

NACK: Not Acknowledged if 1

Start

Condition

Stop

Condition

DATA: 8 Bits (Byte)

Write Operation

Transmitter

Data Type

M

S

M

S

M

S

M

Sp

St

Slave Address

ACK

DATA

ACK

DATA

ACK

W

Read Operation

Transmitter

Data Type

M

S

M

S

M

Sp

St

Slave Address

R

ACK

DATA

ACK

DATA

ACK

NACK

M: Master Device

S: Slave Device

St: Start Condition

Sp: Stop Condition

R: Read

W: Write

ACK: Acknowledge

NACK: Not Acknowledged

Figure 45. Basic I²C Framework

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Write Register

A master can write to any PCM1795 registers using single or multiple accesses. The master sends a PCM1795

slave address with a write bit, a register address, and the data. If multiple access is required, the address is that

of the starting register, followed by the data to be transferred. When the data are received properly, the index

register is incremented by '1' automatically. When the index register reaches 0x7F, the next value is 0x00. When

undefined registers are accessed, the PCM1795 does not send an acknowledgment. Figure 46 shows a diagram

of the write operation.

S

Transmitter

Data Type

M

S

M

S

M

S

M

Register Address

Sp

St

Slave Address

ACK

Write Data 1

ACK Write Data 2 ACK

NACK

W

M: Master Device

S: Slave Device

St: Start Condition

Sp: Stop Condition

ACK: Acknowledge

NACK: Not Acknowledged

W: Write

Figure 46. Write Operation

Read Register

A master can read the PCM1795 register. The value of the register address is stored in an indirect index register

in advance. The master sends a PCM1795 slave address with a read bit after storing the register address. Then

the PCM1795 transfers the data that the index register points to. When the data are transferred during a multiple

access, the index register is incremented by '1' automatically. (When first going into read mode immediately

following a write, the index register is not incremented. The master can read the register that was previously

written.) When the index register reaches 0x7F, the next value is 0x00. The PCM1795 outputs some data when

the index register is 0x10 to 0x1F, even if it is not defined in Table 9. Figure 47 shows a diagram of the read

operation.

S

Transmitter

Data Type

M

S

M

S

M

Register Address

Sp

St

Slave Address

ACK

ACK Sr

Slave Address

R

ACK

Data

ACK

NACK

W

M: Master Device

S: Slave Device

St: Start Condition

Sr: Repeated Start Condition

Sp: Stop Condition

R: Read

W: Write

ACK: Acknowledge

NACK: Not Acknowledged

Figure 47. Read Operation

Noise Suppression

The PCM1795 incorporates noise suppression using the system clock (SCK). However, there must be no more

than two noise spikes in 600 ns. The noise suppression works for SCK frequencies between 8 MHz and 40 MHz

in fast mode. However, it works incorrectly under the following conditions:

Case 1:

1. t_(SCK)> 120 ns (t_(SCK): period of SCK)

2. t_(HI)+ t_(D–HD)< t_(SCK)× 5

3. Spike noise exists on the first half of the SCL high pulse.

4. Spike noise exists on the SDA high pulse just before SDA goes low.

SCL

Noise

SDA

Figure 48. Case 1

When these conditions occur at the same time, the data are recognized as low.

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Case 2:

1. t_(SCK)> 120 ns

2. t_(S–HD)or t_(RS–HD)< t_(SCK)× 5

3. Spike noise exists on both SCL and SDA during the hold time.

SCL

Noise

SDA

Figure 49. Case 2

When these conditions occur at the same time, the PCM1795 fails to detect a start condition.

Case 3:

1. t_(SCK)< 50 ns

2. t_(SP)> t_(SCK)

3. Spike noise exists on SCL just after SCL goes low.

4. Spike noise exists on SDA just before SCL goes low.

SCL

SDA

Noise

Figure 50. Case 3

When these conditions occur at the same time, the PCM1795 erroneously detects a start or stop condition.

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MODE CONTROL REGISTERS

User-Programmable Mode Controls

The PCM1795 includes a number of user-programmable functions that are accessed via mode control registers.

The registers are programmed using the serial control interface, as previously discussed in the SPI Interface and

I₂C Interface sections. Table 8 lists the available mode-control functions, along with the default reset conditions

and associated register index.

Table 8. User-Programmable Function Controls

DF

FUNCTION

Digital attenuation control

DEFAULT

REGISTER

Register 16

Register 17

BIT

PCM

DSD

BYPASS

ATL[7:0] (for left channel)

ATR[7:0] (for right channel)

0 dB

Yes

No

0 dB to –120 dB and mute, 0.5-dB step

Attenuation load control

Attenuation disabled

24-bit I²S format

Register 18

ATLD

Yes

No

Disabled, enabled

Input audio data format selection

16-, 20-, 32-bit standard (right-justified)

format

Register 18

FMT[2:0]

Yes

24-bit MSB-first left-justified format

16-/32-bit I²S format

Sampling rate selection for de-emphasis

Disabled, 44.1 kHz, 48 kHz, 32 kHz

De-emphasis control

De-emphasis disabled

Mute disabled

Normal

Register 18

Register 19

Register 20

DMF[1:0]

DME

Yes

Yes⁽¹⁾

No

Disabled, enabled

Soft mute control

MUTE

REV

No

Soft mute disabled, enabled

Output phase reversal

Yes

No

Yes

No

Normal, reverse

Attenuation speed selection

×1f_S, ×(1/2)f_S, ×(1/4)f_S, ×(1/8)f_S

DAC operation control

×1 f_S

ATS[1:0]

OPE

DAC operation enabled

Monaural

Yes

No

Yes

No

Enabled, disabled

Stereo DF bypass mode select

Monaural, stereo

DFMS

FLT

Digital filter roll-off selection

Sharp roll-off, slow roll-off

Infinite zero mute control

Disabled, enabled

Sharp roll-off

Disabled

No

INZD

No

Yes

No

System reset control

Normal operation

Disabled

SRST

DSD

Yes

No

Reset operation, normal operation

DSD interface mode control

DSD enabled, disabled

Digital-filter bypass control

DF enabled, DF bypass

Monaural mode selection

Stereo, monaural

DF enabled

Stereo

DFTH

MONO

CHSL

OS[1:0]

Yes

Yes⁽²⁾

Channel selection for monaural mode data

Left channel, Right channel

ΔΣ oversampling rate selection

×64 f_S, ×128 f_S, ×32 f_S

Left channel

×64 f_S

PCM zero output enable

DSD zero output enable

Enabled

Disabled

Register 21

PCMZ

Yes

No

Yes

No

DZ[1:0]

Yes

(1) When in DSD mode, DMF[1:0] is defined as DSD filter (analog FIR) performance selection.

(2) When in DSD mode, OS[1:0] is defined as DSD filter (analog FIR) operating rate selection.

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Table 8. User-Programmable Function Controls (continued)

DF

FUNCTION

FUNCTION AVAILABLE ONLY FOR READ

Zero detection flag

DEFAULT

REGISTER

BIT

PCM

DSD

BYPASS

Not zero = 0

ZFGL (for left channel)

ZFGR (for right channel)

ID[4:0]

Register 22

Register 23

Yes

No

Yes

No

Not zero, zero detected

Zero detected = 1

—

Device ID (at TDMCA)

Register Map

The mode control register map is shown in Table 9. Registers 16 to 21 include an R/W bit that determines

whether a register read (R/W = 1) or write (R/W = 0) operation is performed. Registers 22 and 23 are read-only.

Table 9. Mode Control Register Map

REGISTER

Register 16

Register 17

Register 18

Register 19

Register 20

Register 21

Register 22

Register 23

B15

R/W

R

B14

0

B13

0

B12

1

B11

0

B10

0

B9

0

B8

0

B7

B6

B5

B4

B3

B2

B1

B0

ATL7

ATL6

ATL5

ATL4

ATL3

ATL2

ATL1

ATL0

0

1

0

1

ATR7 ATR6 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0

0

1

0

1

0

ATLD FMT2 FMT1 FMT0 DMF1 DMF0

DME

FLT

MUTE

INZD

OS0

0

1

0

1

REV

RSV

ATS1

SRST

RSV

ATS0

DSD

RSV

OPE

RSV

DFMS

0

1

0

1

0

DFTH MONO CHSL

OS1

DZ0

0

1

0

1

0

1

RSV

ID4

RSV

ID3

DZ1

RSV

ID2

PCMZ

0

1

0

1

0

RSV

ZFGR ZFGL

ID1 ID0

R

0

1

0

1

RSV

Register Definitions

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

B15

Register 16

Register 17

0

1

0

1

ATL7

ATL6

ATL5

ATL4

ATR4

ATL3

ATR3

ATL2

ATR2

ATL1

ATR1

ATL0

ATR0

R/W

0

1

0

ATR7

ATR6

ATR5

R/W

R/W: Read/Write Mode Select

When R/W = 0, a write operation is performed.

When R/W = 1, a read operation is performed.

Default value: 0

ATx[7:0]: Digital Attenuation Level Setting

These bits are available for read and write.

Default value: 1111 1111b

Each DAC output has a digital attenuator associated with it. The attenuator can be set from 0 dB to –120 dB, in

0.5-dB steps. Alternatively, the attenuator can be set to infinite attenuation (or mute). The attenuation data for

each channel can be set individually. However, the data load control (the ATLD bit of control register 18) is

common to both attenuators. ATLD must be set to '1' in order to change an attenuator setting. The attenuation

level can be set using Equation 1:

Attenuation level (dB) = 0.5 dB × (ATx[7:0]_DEC– 255)

Where,

ATx[7:0]_DEC= 0 through 255

For ATx[7:0]_DEC= 0 through 14, the attenuator is set to infinite attenuation. Table 10 lists the attenuation levels

for various settings.

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Table 10. Attenuation Levels

ATx[7:0]

1111 1111b

1111 1110b

1111 1101b

—

DECIMAL VALUE

ATTENUATION LEVEL SETTING

0 dB, no attenuation (default)

255

254

253

—

–0.5 dB

–1.0 dB

—

0001 0000b

0000 1111b

0000 1110b

—

16

15

14

—

–119.5 dB

–120.0 dB

Mute

—

0000 0000b

0

Mute

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

B15

Register 18

0

1

0

1

0

ATLD

FMT2 FMT1 FMT0 DMF1 DMF0

DME MUTE

R/W

R/W: Read/Write Mode Select

When R/W = 0, a write operation is performed.

When R/W = 1, a read operation is performed.

Default value: 0

ATLD: Attenuation Load Control

This bit is available for read and write.

Default value: 0

ATLD

Attenuation Control Setting

ATLD = 0

ATLD = 1

Attenuation control disabled (default)

Attenuation control enabled

The ATLD bit is used to enable loading of the attenuation data contained in registers 16 and 17. When ATLD =

0, the attenuation settings remain at the previously programmed levels, ignoring new data loaded from registers

16 and 17. When ATLD = 1, attenuation data written to registers 16 and 17 is loaded normally.

FMT[2:0]: Audio Interface Data Format

These bits are available for read and write.

Default value: 101

FMT[2:0]

000

Audio Data Format Selection

16-bit standard format, right-justified data, BCK ≥ x32 f_S

32-bit standard format, right-justified data, BCK ≥ x64 f_S

24-bit standard format, right-justified data, BCK ≥ x48 f_S

24-bit MSB-first, left-justified format data, BCK ≥ x48 f_S

32-bit I²S format data, BCK ≥ x64 f_S

001

010

011

100

101

24-bit I²S format data (default), BCK ≥ x48 f_S

110

Reserved

111

Reserved

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The FMT[2:0] bits are used to select the data format for the serial audio interface.

For the external digital filter interface mode (DFTH mode), this register is operated as shown in the Application

for External Digital Filter Interface section.

DMF[1:0]: Sampling Frequency Selection for the De-Emphasis Function

These bits are available for read and write.

Default value: 00

DMF[1:0]

De-Emphasis Sampling Frequency Selection

00

01

10

11

Disabled (default)

48 kHz

44.1 kHz

32 kHz

The DMF[1:0] bits are used to select the sampling frequency used by the digital de-emphasis function when it is

enabled by setting the DME bit. The de-emphasis curves are shown in the Typical Characteristics section.

For the DSD mode, analog FIR filter performance can be selected using this register. A register map and filter

response plots are shown in the Application For DSD Format (DSD Mode) Interface section.

DME: Digital De-Emphasis Control

This bit is available for read and write.

Default value: 0

DME

De-Emphasis Setting

DME = 0

DME = 1

De-emphasis disabled (default)

De-emphasis enabled

The DME bit is used to enable or disable the de-emphasis function for both channels.

MUTE: Soft Mute Control

This bit is available for read and write.

Default value: 0

MUTE

Soft Mute Setting

MUTE = 0

MUTE = 1

Soft mute disabled (default)

Soft mute enabled

The MUTE bit is used to enable or disable the soft mute function for both channels.

Soft mute is operated as a 256-step attenuator. The speed for each step to –∞ dB (mute) is determined by the

attenuation rate selected in the ATS register.

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

B15

Register 19

0

1

0

1

REV

ATS1

ATS0

OPE

RSV

DMFS

FLT

INZD

R/W

R/W: Read/Write Mode Select

When R/W = 0, a write operation is performed.

When R/W = 1, a read operation is performed.

Default value: 0

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REV: Output Phase Reversal

This bit is available for read and write.

Default value: 0

REV

Output Setting

REV = 0

REV = 1

Normal output (default)

Inverted output

The REV bit is used to invert the output phase for both channels.

ATS[1:0]: Attenuation Rate Select

These bits are available for read and write.

Default value: 00

ATS[1:0]

Attenuation Rate Selection

00

01

10

11

Every LRCK (default)

LRCK/2

LRCK/4

LRCK/8

The ATS[1:0] bits are used to select the rate at which the attenuator is decremented/incremented during level

transitions.

OPE: DAC Operation Control

This bit is available for read and write.

Default value: 0

OPE

DAC Operation Control

OPE = 0

OPE = 1

DAC operation enabled (default)

DAC operation disabled

The OPE bit is used to enable or disable the analog output for both channels. Disabling the analog outputs

forces them to the bipolar zero level (BPZ) even if audio data are present on the input.

DFMS: Stereo DF Bypass Mode Select

This bit is available for read and write.

Default value: 0

DFMS

Mode Selection

DFMS = 0

DFMS = 1

Monaural (default)

Stereo input enabled

The DFMS bit is used to enable stereo operation in DF bypass mode. In the DF bypass mode, when DFMS is

set to '0', the pin for the input data are DATA (pin 5) only; therefore, the PCM1795 operates as a monaural DAC.

When DFMS is set to '1', the PCM1795 can operate as a stereo DAC with inputs of the left channel and right

channel data on ZEROL (pin 1) and ZEROR (pin 2), respectively.

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FLT: Digital Filter Roll-Off Control

This bit is available for read and write.

Default value: 0

FLT

Roll-Off Control

FLT = 0

FLT = 1

Sharp roll-off (default)

Slow roll-off

The FLT bit is used to select the digital filter roll-off characteristic. The filter responses for these selections are

shown in the Typical Characteristics section.

INZD: Infinite Zero Detect Mute Control

This bit is available for read and write.

Default value: 0

INZD

Infinite Zero Detect Mute Setting

Infinite zero detect mute disabled (default)

Infinite zero detect mute enabled

INZD = 0

INZD = 1

The INZD bit is used to enable or disable the zero detect mute function. Setting INZD to '1' forces muted analog

outputs to hold a bipolar zero level when the PCM1795 detects a zero condition in both channels. The infinite

zero detect mute function is not available in the DSD mode.

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

B15

Register 20

0

1

0

1

0

RSV

SRST

DSD

DFTH MONO CHSL

OS1

OS0

R/W

R/W: Read/Write Mode Select

When R/W = 0, a write operation is performed.

When R/W = 1, a read operation is performed.

Default value: 0

SRST: System Reset Control

This bit is available for write only.

Default value: 0

SRST

System Reset Control

SRST = 0

SRST = 1

Normal operation (default)

System reset operation (generate one reset pulse)

The SRST bit is used to reset the PCM1795 to the initial system condition.

DSD: DSD Interface Mode Control

This bit is available for read and write.

Default value: 0

DSD

DSD Interface Mode Control

DSD = 0

DSD = 1

DSD interface mode disabled (default)

DSD interface mode enabled

The DSD bit is used to enable or disable the DSD interface mode.

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DFTH: Digital Filter Bypass (or Through Mode) Control

This bit is available for read and write.

Default value: 0

DFTH

Digital Filter Control

DFTH = 0

DFTH = 1

Digital filter enabled (default)

Digital filter bypassed for external digital filter

The DFTH bit is used to enable or disable the external digital filter interface mode.

MONO: Monaural Mode Selection

This bit is available for read and write.

Default value: 0

MONO

Mode Selection

MONO = 0

MONO = 1

Stereo mode (default)

Monaural mode

The MONO function is used to change operation mode from the normal stereo mode to the monaural mode.

When the monaural mode is selected, both DACs operate in a balanced mode for one channel of audio input

data. Channel selection is available for left-channel or right-channel data, determined by the CHSL bit.

CHSL: Channel Selection for Monaural Mode

This bit is available for read and write.

Default value: 0

CHSL

Channel Selection

CHSL = 0

CHSL = 1

Left channel selected (default)

Right channel selected

This bit is available when MONO = 1.

The CHSL bit selects left-channel or right-channel data to be used in monaural mode.

OS[1:0]: ΔΣ Oversampling Rate Selection

These bits are available for read and write.

Default value: 00

OS[1:0]

00

Operating Speed Selection

64 times f_S(default)

32 times f_S

01

10

128 times f_S

Reserved

11

The OS bits are used to change the oversampling rate of ΔΣ modulation. Use of this function enables the

designer to stabilize the conditions at the post low-pass filter for different sampling rates. As an application

example, programming to set 128 times in 44.1-kHz operation, 64 times in 96-kHz operation, or 32 times in

192-kHz operation allows the use of only a single type (cut-off frequency) of post low-pass filter. The 128-f_S

oversampling rate is not available at sampling rates above 100 kHz. If the 128-f_Soversampling rate is selected, a

system clock of more than 256 f_Sis required.

In DSD mode, these bits are used to select the speed of the bit clock for DSD data coming into the analog FIR

filter.

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B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

B15

Register 21

0

1

0

1

0

1

RSV

DZ1

DZ0

PCMZ

R/W

R/W: Read/Write Mode Select

When R/W = 0, a write operation is performed.

When R/W = 1, a read operation is performed.

Default value: 0

DZ[1:0]: DSD Zero Output Enable

These bits are available for read and write.

Default value: 00

DZ[1:0]

Zero Output Enable

00

01

Disabled (default)

Even pattern detect 1 × 96h pattern detect

The DZ bits are used to enable or disable the output zero flags and to select the zero pattern in DSD mode.

PCMZ: PCM Zero Output Enable

These bits are available for read and write.

Default value: 1

PCMZ

PCM Zero Output Setting

PCMZ = 0

PCMZ = 1

PCM zero output disabled

PCM zero output enabled (default)

The PCMZ bit is used to enable or disable the output zero flags in PCM mode and the external DF mode.

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

B15

Register 22

0

1

0

1

0

RSV

ZFGR ZFGL

R

R: Read Mode Select

Value is always '1', specifying the readback mode.

ZFGx: Zero-Detection Flag

Where x = L or R, corresponding to the DAC output channel. These bits are available only for readback.

Default value: 00

ZFGx

Zero Detection

ZFGx = 0

ZFGx = 1

Not zero

Zero detected

These bits show zero conditions. The status is the same as that of the zero flags at ZEROL (pin 1) and ZEROR

(pin 2). See Zero Detect in the Function Descriptions section.

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B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

B15

Register 23

0

1

0

1

RSV

ID4

ID3

ID2

ID1

ID0

R

Read Mode Select

Value is always '1', specifying the readback mode.

ID[4:0]: Device ID

The ID[4:0] bits hold a device ID in the TDMCA mode.

APPLICATION INFORMATION

TYPICAL CONNECTION DIAGRAM IN PCM MODE

Figure 51 shows a typical application circuit for PCM mode operation.

C_F

R_F

5 V

0.1 mF

ZEROL

ZEROR

MSEL

LRCK

DATA

BCK

V_CC2L

AGND3L

I_OUTL–

1

2

28

27

26

25

24

23

22

21

20

19

18

17

16

15

+

10 mF

–

+

Differential-

to-Single

Converter

With

3

C_F

R_F

V_OUT

I_OUTL+

4

Left Channel

5 V

Low-Pass

Filter

PCM

Audio

Data

AGND2

5

–

V_CC

V_COM

I_REF

1

6

Source

+

47 mF

+

SCK

L

7

C_F

R_F

10 mF

PCM1796

DGND

V_DD

R

8

0.1 mF

10 kW

9

–

MS

AGND1

I_OUTR–

10

11

12

13

14

+

Differential-

to-Single

Converter

With

MDI

C_F

R_F

V_OUT

Controller

MC

I_OUTR+

Right Channel

0.1 mF

Low-Pass

Filter

AGND3R

V_CC2R

MDO

RST

–

+

5 V

10 mF

+

10 mF

3.3 V

Figure 51. Typical Application Circuit for Standard PCM Audio Operation

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APPLICATION CIRCUIT

The design of the application circuit is very important in order to actually realize the high S/N ratio of which the

PCM1795 is capable, because noise and distortion that are generated in an application circuit are not negligible.

In the third-order, low-pass filter (LPF) circuit of Figure 52, the output level of 2.1 V RMS and 123-dB

signal-to-noise ratio is achieved.

Figure 53 shows a circuit for the DSD mode, which is a fourth-order LPF in order to reduce the out-of-band

noise.

I/V Section

The current of the PCM1795 on each of the output pins (I_OUTL+, I_OUTL–, I_OUTR+, I_OUTR–) is 4 mA_PPat 0 dB

(full-scale). The voltage output level of the current-to-voltage (I/V) converter, V_I, is given by Equation 2:

V_I= 4 mA_PP× R_F

Where:

R_F= feedback resistance of the I/V converter

An NE5534 operational amplifier is recommended for the I/V circuit to obtain the specified performance. Dynamic

performance such as the gain bandwidth, settling time, and slew rate of the operational amplifier affects the

audio dynamic performance of the I/V section.

Differential Section

The PCM1795 voltage outputs are followed by differential amplifier stages that sum the differential signals for

each channel, creating a single-ended I/V op-amp output. In addition, the differential amplifiers provide a

low-pass filter function.

The operational amplifier recommended for the differential circuit is the low-noise type.

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C₁

2700 pF

R₁

820 W

V_CC

C₁₁

0.1 mF

R₅

C₁₅

C₃

200 W

0.1 mF

8200 pF

C₁₇

22 pF

7

C₁₉

5

R₃

R₇

22 pF

7

2

3

8

6

I_OUT-

–

220 W

5

180 W

R₉

2

3

8

6

–

100 W

C₅

27000 pF

+

U₁

NE5534

+

U₃

4

NE5534

C₁₂

4

R₄

R₈

0.1 mF

C₁₆

220 W

180 W

R₆

200 W

0.1 mF

C₄

V_EE

8200 pF

V_EE

C₂

2700 pF

R₂

820 W

V_CC

C₁₃

0.1 mF

C₁₈

22 pF

7

5

2

3

8

6

I_OUT+

–

+

U₂

NE5534

4

C₁₄

0.1 mF

V_EE

Figure 52. Measurement Circuit for PCM

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C₁

2200 pF

R₁

820 W

V_CC

C₁₁

0.1 mF

R₅

C₁₅

C₅

150 W

0.1 mF

8200 pF

C₁₇

22 pF

7

C₁₉

5

R₃

R₈

R₁₀

22 pF

7

2

3

8

6

I_OUT-

–

91 W

75 W

5

120 W

R₇

2

3

8

6

–

100W

C₃

C₄

27000 pF

+

U₁

22000 pF

NE5534

+

U₃

4

NE5534

C₁₂

4

R₄

R₉

R₁₁

0.1 mF

C₁₆

91 W

75 W

120 W

R₆

150 W

0.1 mF

C₆

V_EE

8200 pF

V_EE

C₂

2200 pF

R₂

820 W

V_CC

C₁₃

0.1 mF

C₁₈

22 pF

7

5

2

3

8

6

I_OUT+

–

+

U₂

NE5534

4

C₁₄

0.1 mF

V_EE

Figure 53. Measurement Circuit for DSD

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I_OUTL- (Pin 26)

I_OUT

-

OUT+

Circuit⁽¹⁾

I_OUTL+ (Pin 25)

I_OUT+

3

2

1

I_OUTR- (Pin 18)

I_OUT

-

OUT-

Circuit⁽¹⁾

Balanced Out

I_OUTR+ (Pin 17)

I_OUT+

(1) Circuit corresponds to Figure 52.

Figure 54. Measurement Circuit for Monaural Mode

APPLICATION FOR EXTERNAL DIGITAL FILTER INTERFACE

Figure 55 shows the connection diagram for an external digital filter.

DFMS = 0

External Filter Device

PCM1796

1

2

3

4

5

6

7

ZEROL

ZEROR

MSEL

LRCK

DATA

BCK

WDCK (Word Clock)

DATA

BCK

SCK

DFMS = 1

External Filter Device

DATA_L

PCM1796

1

2

3

4

5

6

7

ZEROL

ZEROR

MSEL

LRCK

DATA

DATA_R

WDCK (Word Clock)

BCK

SCK

BCK

SCK

Figure 55. Connection Diagram for External Digital Filter (Internal DF Bypass Mode) Application

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Application for Interfacing With an External Digital Filter

For some applications, it may be desirable to use an external digital filter to perform the interpolation function, as

it can provide improved stop-band attenuation when compared to the internal digital filter of the PCM1795.

The PCM1795 supports several external digital filters, including:

•

Texas Instruments DF1704 and DF1706

Pacific Microsonics PMD200 HDCD filter/decoder IC

Programmable digital signal processors (DSPs)

The external digital filter application mode is accessed by programming the following bits in the corresponding

control register:

•

DFTH = 1 (register 20)

The pins used to provide the serial interface for the external digital filter are illustrated in Figure 55. The word

clock (WDCK) signal must be operated at 8 times or 4 times the desired sampling frequency, f_S.

Pin Assignment When Using the External Digital Filter Interface

•

LRCK (pin 4): WDCK as word clock input

BCK (pin 6): Bit clock for audio data

DATA (pin 5): Monaural audio data input when the DFMS bit is not set to '1'

ZEROL (pin 1): DATAL as left channel audio data input when the DFMS bit is set to '1'

ZEROR (pin 2): DATAR as right channel audio data input when the DFMS bit is set to '1'

Audio Format

The PCM1795 in the external digital filter interface mode supports right-justified audio formats including 16-bit,

24-bit, and 32-bit audio data, as shown in Figure 56. The audio format is selected by the FMT[2:0] bits of control

register 18.

1/4 f_Sor 1/8 f_S

WDCK

BCK

Audio Data Word = 16-Bit

DATA,DATAL, DATAR

15 16

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16

MSB

LSB

Audio Data Word = 32-Bit

DATA,DATAL, DATAR

31 32

1

2

3

4

5

19 20 21 22 23 24 25 26 27 28 29 30 31 32

MSB

LSB

Audio Data Word = 24-Bit

DATA,DATAL, DATAR

23 24

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

MSB

LSB

Figure 56. Audio Data Input Format for External Digital Filter (Internal DF Bypass Mode) Application

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System Clock (SCK) and Interface Timing

The PCM1795 in an application using an external digital filter requires the synchronization of WDCK and the

system clock. The system clock is phase-free with respect to WDCK. Interface timing among WDCK, BCK,

DATA, DATAL, and DATAR is shown in Figure 57 and Table 11.

WDCK

1.4 V

t_(BCH)

t_(BCL)

t_(LB)

BCK

t_(BCY)

t_(BL)

DATA

DATAL

DATAR

t_(DS)

t_(DH)

Figure 57. Audio Interface Timing for External Digital Filter (Internal DF Bypass Mode) Application

Table 11. Timing Characteristics for Figure 57

PARAMETER

BCK pulse cycle time

MIN

20

7

MAX

UNIT

ns

t_(BCY)

t_(BCL)

t_(BCH)

t_(BL)

BCK pulse duration, low

ns

BCK pulse duration, high

7

ns

BCK rising edge to WDCK falling edge

WDCK falling edge to BCK rising edge

DATA, DATAL, DATAR setup time

DATA, DATAL, DATAR hold time

5

ns

t_(LB)

5

ns

t_(DS)

t_(DH)

5

ns

5

ns

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FUNCTIONS AVAILABLE IN THE EXTERNAL DIGITAL FILTER MODE

The external digital filter mode is selected by setting DSD = 0 (register 20, B5) and DFTH = 1 (register 20, B4).

The external digital filter mode allows access to the majority of the PCM1795 mode control functions.

Table 12 shows the register mapping available when the external digital filter mode is selected, along with

descriptions of functions that are modified when using this mode selection.

Table 12. External Digital Filter Register Map

REGISTER

Register 16

Register 17

Register 18

Register 19

Register 20

Register 21

Register 22

B15

R/W

R

B14

0

B13

0

B12

1

B11

0

B10

0

B9

0

B8

0

B7

X⁽¹⁾

X

B6

X

B5

X

B4

X

B3

X

B2

B1

X

B0

X

0

1

0

1

X

0

1

0

1

0

X

FMT2 FMT1 FMT0

X

0

1

0

1

REV

X

SRST

X

0

OPE

1

X

DFMS

X

INZD

OS0

PCMZ

0

1

0

1

0

MONO CHSL

OS1

X

0

1

0

1

0

1

X

0

1

0

1

0

X

ZFGR ZFGL

(1) Function is disabled. No operation even if data bit is set.

FMT[2:0]: Audio Data Format Selection

Default value: 000

FMT[2:0]

Audio Data Format Selection

000

001

16-bit right-justified format

32-bit right-justified format

010

24-bit right-justified format (default)

N/A

Other

OS[1:0]: ΔΣ Modulator Oversampling Rate Selection

Default value: 00

OS[1:0]

Operation Speed Selection

00

01

10

11

8 times WDCK (default)

4 times WDCK

16 times WDCK

Reserved

The effective oversampling rate is determined by the oversampling performed by both the external digital filter

and the ΔΣ modulator. For example, if the external digital filter is 8× oversampling, and OS[1:0] = 00 is selected,

then the ΔΣ modulator oversamples by 8×, resulting in an effective oversampling rate of 64×. The 16× WDCK

oversampling rate is not available above a 100-kHz sampling rate. If the oversampling rate selected is 16×

WDCK, the system clock frequency must be over 256 f_S.

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APPLICATION FOR DSD FORMAT (DSD MODE) INTERFACE

Figure 58 shows a connection diagram for DSD mode.

DSD Decoder

PCM1796

1

2

3

4

5

6

7

ZEROL

ZEROR

MSEL

LRCK

DATA

DATA_R

DATA_L

BCK

Bit Clock

SCK

Figure 58. Connection Diagram in DSD Mode

Feature

This mode is used for interfacing directly to a DSD decoder, which is found in Super Audio CD™ (SACD)

applications.

The DSD mode is accessed by programming the following bit in the corresponding control register.

•

DSD = 1 (register 20)

The DSD mode provides a low-pass filtering function. The filtering is provided using an analog FIR filter structure.

Four FIR responses are available and are selected by the DMF[1:0] bits of control register 18.

The DSD bit must be set before inputting DSD data; otherwise, the PCM1795 erroneously detects the TDMCA

mode and commands are not accepted through the serial control interface.

Pin Assignment When Using DSD Format Interface

Several pins are redefined for DSD mode operation. These include:

•

DATA (pin 5): DSDL as left-channel DSD data input

LRCK (pin 4): DSDR as right-channel DSD data input

SCK (pin 7): DBCK as bit clock for DSD data

BCK (pin 6): Set low (N/A)

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Requirements for System Clock

For operation in DSD mode, the bit clock (DBCK) is required on pin 7 of the PCM1795. The frequency of the bit

clock can be N times the sampling frequency. Generally, N is 64 in DSD applications.

The interface timing between the bit clock and DSDL and DSDR is required to meet the setup and hold time

specifications shown in Figure 60 and Table 13.

t = 1/(64 ´ 44.1 kHz)

DBCK

DSDL,

DSDR

D0

D1

D2

D3

D4

Figure 59. Normal Data Output Form From DSD Decoder

t_(BCH)

t_(BCL)

DBCK

1.4 V

t_(BCY)

DSDL,

DSDR

t_(DS)

t_(DH)

Figure 60. Timing for DSD Audio Interface

Table 13. Timing Characteristics for Figure 60

PARAMETER

MIN

85⁽¹⁾

30

MAX

UNIT

t_(BCY)

t_(BCH)

t_(BCL)

t_(DS)

DBCK pulse cycle time

DBCK high-level time

DBCK low-level time

ns

30

DSDL, DSDR setup time

DSDL, DSDR hold time

10

t_(DH)

10

(1) 2.8224 MHz × 4. (2.8224 MHz = 64 × 44.1 kHz. This value is specified as a sampling rate of DSD.

DSD MODE CONFIGURATION AND FUNCTION CONTROLS

Configuration for the DSD Interface Mode

The DSD interface mode is selected by setting DSD = 1 (register 20, B5).

Table 14. DSD Mode Register Map

REGISTER

Register 16

Register 17

Register 18

Register 19

Register 20

Register 21

Register 22

B15

R/W

R

B14

0

B13

0

B12

1

B11

0

B10

0

B9

0

B8

0

B7

X⁽¹⁾

X

B6

B5

X

1

B4

X

B3

X

B2

B1

B0

X

0

1

0

1

X

0

1

0

1

0

X

DMF1 DMF0

X

0

1

0

1

REV

X

OPE

X

0

1

0

1

0

SRST

X

MONO CHSL

OS1

DZ0

OS0

X

0

1

0

1

0

1

X

DZ1

X

R

0

1

0

1

0

X

ZFGR ZFGL

(1) Function is disabled. No operation even if data bit is set.

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DMF[1:0]: Analog-FIR Performance Selection

Default value: 00

DMF[1:0]

Analog-FIR Performance Selection

00

01

10

11

FIR-1 (default)

FIR-2

FIR-3

FIR-4

Plots for the four analog finite impulse response (FIR) filter responses are shown in the Analog FIR Filter

Performance in DSD Mode section of the Typical Characteristics.

OS[1:0]: Analog-FIR Operation-Speed Selection

Default value: 00

OS[1:0]

00

Operating Speed Selection

f_DBCK(default)

f_DBCK/2

01

10

Reserved

f_DBCK/4

11

The OS bit in the DSD mode is used to select the operating rate of the analog FIR. The OS bits must be set

before setting the DSD bit to '1'.

TDMCA INTERFACE FORMAT

The PCM1795 supports the time-division-multiplexed command and audio (TDMCA) data format to simplify the

host control serial interface. TDMCA format is designed not only for the multichannel buffered serial port

description (McBSP) of TI DSPs but also for any programmable devices. TDMCA format can transfer not only

audio data but also command data, so that it can be used together with any kind of device that supports TDMCA

format. The TDMCA frame consists of a command field, extended command field, and some audio data fields.

Those audio data are transported to IN devices (such as a DAC) and/or from OUT devices (such as an ADC).

The PCM1795 is an IN device. LRCK and BCK are used with both IN and OUT devices so that the sample

frequency of all devices in a system must be the same. The TDMCA mode supports a maximum of 30 device

IDs. The maximum number of audio channels depends on the BCK frequency.

TDMCA Mode Determination

The PCM1795 recognizes the TDMCA mode automatically when it receives an LRCK signal with a pulse

duration of two BCK clocks. If the TDMCA mode operation is not needed, the duty cycle of LRCK must be 50%.

Figure 61 shows the LRCK and BCK timing that determines the TDMCA mode. The PCM1795 enters TDMCA

mode after two continuous TDMCA frames. Any TDMCA commands can be issued during the next TDMCA

frame after entering TDMCA mode.

Command

Accept

Pre-TDMCA Frame

TDMCA Frame

LRCK

BCK

2 BCKs

Figure 61. LRCK and BCK Timing for Determination of TDMCA Mode

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TDMCA Terminals

TDMCA requires six signals: four signals are for the command and audio data interface, and one pair for

daisy-chaining. These signals can be shared as shown in Table 15. The DO signal has a 3-state output so that it

can be connected directly to other devices.

Table 15. TDMCA Terminals

TERMINAL NAME

TDMCA NAME

PROPERTY

DESCRIPTION

TDMCA frame start signal; it must be the same as the sampling

frequency

LRCK

Input

TDMCA clock; its frequency must be high enough to communicate a

TDMCA frame within an LRCK cycle

BCK

Input

DATA

MDO

MC

DI

DO

Input

Output

Input

TDMCA command and audio data input signal

TDMCA command data 3-state output signal

TDMCA daisy-chain input signal

DCI

DCO

MS

Output

TDMCA daisy-chain output signal

Device ID Determination

TDMCA mode also supports a multichip implementation in one system. This capability means that a host

controller (DSP) can simultaneously support several TDMCA devices, which can be of the same type or different

types, including PCM devices. The PCM devices are categorized as either IN devices, OUT devices, IN/OUT

devices, and NO devices. The IN device has an input port to receive audio data; the OUT device has an output

port to supply audio data; the IN/OUT device has both input and output ports for audio data; and the NO device

has no port for audio data, but requires command data from the host. A DAC is an IN device; an ADC is an OUT

device; a codec is an IN/OUT device; and a PLL is a NO device. The PCM1795 is an IN device. For the host

controller to distinguish the devices, each device is assigned its own device ID by the daisy-chain. The devices

obtain their own device IDs automatically by connecting the DCI to the DCO of the preceding device and the

DCO to the DCI of the following device in the daisy-chain. The daisy-chains are categorized as the IN chain and

the OUT chain, which are completely independent and equivalent. Figure 62 shows an example daisy-chain

connection. If a system must chain the PCM1795 and a NO device in the same IN or OUT chain, the NO device

must be chained at the back end of the chain because it does not require any audio data. Figure 63 shows an

example TDMCA system including an IN chain and an OUT chain with a TI DSP. For a device to get its own

device ID, the DID signal must be set to '1' (see the Command Field section for details), and LRCK and BCK

must be driven in the TDMCA mode for all PCM devices that are chained. The device at the top of the chain

knows its device ID is '1' because its DCI is fixed high. Other devices count the BCK pulses and observe the

respective DCI signal to determine ID and position in the chain. Figure 64 shows the initialization of each device

ID.

IN Chain

¼

IN

IN Device

NO Device

IN/OUT

Device

IN/OUT

Device

¼

OUT Device

OUT

¼

OUT Chain

Figure 62. Daisy-Chain Connection Example

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DCII

LRCK

DCOI

BCK

DI

IN/OUT

Device

(DIX1700)

DCIO

DO

DCOO

Device ID = 1

LRCK

BCK

DI

DCI

IN Device

(PCM1795)

DCO

DO

Device ID = 2

LRCK

BCK

DI

DCI

NO Device

DCO

DO

Device ID = 3

FSX

FSR

LRCK

BCK

DI

DCI

OUT Device

CLKX

CLKR

DX

DCO

DR

DO

Device ID = 2

TI DSP

LRCK

BCK

DI

DCI

OUT Device

DCO

DO

Device ID = 3

Figure 63. IN Daisy-Chain and OUT Daisy-Chain Connection Example for a Multichip System

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LRCK

BCK

DI

DID

Command Field

Device ID = 1

DCO1

DCO1,

DCI2

Device ID = 2

Device ID = 3

DCO2,

DCI3

58 BCKs

DCO29,

DCI30

Device ID = 30

Figure 64. Device ID Determination Sequence

TDMCA Frame

In general, the TDMCA frame consists of the command field, extended command (EMD) field, and audio data

fields. All fields are 32 bits in length, but the lowest byte has no meaning. The MSB is transferred first for each

field. The command field is always transferred as the first packet of the frame. The EMD field is transferred if the

EMD flag of the command field is high. If any EMD packets are transferred, no audio data follow the EMD

packets. This frame is for quick system initialization. All devices of a daisy-chain should respond to the command

field and extended command field. The PCM1795 has two audio channels that can be selected by OPE (register

19). If the OPE bit is not set to high, those audio channels are transferred. Figure 65 shows the general TDMCA

frame. If some DACs are enabled, but corresponding audio data packets are not transferred, the analog outputs

are unpredictable.

1/f_S

LRCK

BCK

[For Initialization]

Don’t

Care

DI

CMD

EMD

CMD

EMD

CMD

EMD

CMD

EMD

CMD

32 Bits

CMD

DO

[For Operation]

Don’t

Care

Ch (n)

Ch (m)

DI

CMD

Ch 1

Ch 2

Ch 3

Ch 4

CMD

DO

Figure 65. General TDMCA Frame

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1/f_S(256 BCK Clocks)

7 Packets ´ 32 Bits

LRCK

BCK

Don’t

Care

DI

CMD

Ch 1

IN and OUT Channel Orders are Completely Independent

Ch 1 Ch 2

Ch 2

Ch 3

Ch 4

Ch 5

Ch 6

CMD

DO

Figure 66. TDMCA Frame Example of Six-Channel DAC and Two-Channel ADC With Command Read

Command Field

The normal command field is defined as shown in Figure 67. When the DID bit (MSB) is '1', this frame is used

only for device ID determination, and all remaining bits in the field are ignored.

31

30

29

28

24

23

22

16 15

8

7

0

Command

DID

EMD

DCS

Device ID

Data

Not Used

Register ID

R/W

Figure 67. Normal Command Field

Bit 31: Device ID enable flag

The PCM1795 operates to get its own device ID for TDMCA initialization if this bit is high.

Bit 30: Extended command enable flag

The EMD packet is transferred if this bit is high; otherwise, it is skipped. Once this bit is high, this frame does not

contain any audio data. This is for system initialization.

Bit 29: Daisy-chain selection flag

A high setting designates OUT-chain devices, low designates IN-chain devices. The PCM1795 is an IN device,

so the DCS bit must be set low.

Bits[28:24]: Device ID

The device ID is five bits in length and it can be defined. These bits identify the order of a device in the IN or

OUT daisy-chain. The top of the daisy-chain defines device ID 1 and successive devices are numbered 2, 3, 4,

etc. All devices for which the DCI is fixed high are also defined as ID 1. The maximum device ID is 30 each in

the IN and OUT chains. If a device ID of 0x1F is used, all devices are selected as broadcast when in the write

mode. If a device ID of 0x00 is used, no device is selected.

Bit 23: Command Read/Write flag

If this bit is high, the command is a read operation.

Bits[22:16]: Register ID

The register ID is seven bits in length.

Bits[15:8]: Command data

The command data are eight bits in length. Any valid data can be chosen for each register.

Bits[7:0]: Not used

These bits are never transported when a read operation is performed.

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Extended Command Field

The extended command field is the same as the command field, except that it does not have a DID flag.

Figure 68 defines the extended command field.

31

30

29

28

24

23

22

16 15

8

7

0

Extended Command

RSVD EMD

DCS

Device ID

Data

Not Used

Register ID

R/W

Figure 68. Extended Command Field

Audio Fields

The audio field is 32 bits in length and the audio data are transferred MSB first, so the other fields must be filled

with 0s as shown in Figure 69.

31

16

12

8

7

4

3

0

Audio Data

MSB

24 Bits

LSB

All 0s

Figure 69. Audio Field Example

TDMCA Register Requirements

The TDMCA mode requires device ID and audio channel information, as previously described. The OPE bit in

register 19 indicates audio channel availability and register 23 indicates the device ID. Register 23 is used only in

the TDMCA mode; see the mode control register map of Table 9.

Register Write/Read Operation

The command supports register write and read operations. If the command requests to read one register, the

read data are transferred on DO during the data phase of the timing cycle. The DI signal can be retrieved at the

positive edge of BCK, and the DO signal is driven at the negative edge of BCK. DO is activated one BCK cycle

early to compensate for the output delay caused by high impedance. Figure 70 shows the TDMCA write and

read timing.

Register ID Phase

Data Phase

BCK

DI

Read Mode and Proper Register ID

Write Data Retrieved, if Write Mode

Read Data Driven, if Read Mode

1 BCK Early

DO

DOEN

(Internal)

Figure 70. TDMCA Write and Read Operation Timing

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TDMCA Mode Operation

DCO specifies the owner of the next audio channel in TDMCA mode operation. When a device retrieves its own

audio channel data, DCO goes high during the last audio channel period. Figure 71 shows the DCO output

timing in TDMCA mode operation. The host controller ignores the behavior of DCI and DCO. DCO indicates the

last audio channel of each device. Therefore, DCI means the next audio channel is allocated.

If some devices are skipped because of no active audio channel, the skipped devices must notify the next device

that the DCO will be passed through the next DCI. Figure 72 and Figure 73 show DCO timing with skip

operation. Figure 74 and Table 16 show the ac timing of the daisy-chain signals.

1/f_S(384 BCK Clocks)

9 Packets ´ 32 Bits

LRCK

BCK

IN Daisy Chain

DI

CMD

Ch 1

Ch 2

Ch 3

Ch 4

Ch 5

Ch 6

Ch 7

Ch 8

Don’t Care

CMD

DCI1

DID = 1

DID = 2

DCO1

DCI2

DCO2

DCI3

DID = 3

DID = 4

DCO3

DCI4

DCO4

Figure 71. DCO Output Timing of TDMCA Mode Operation

1/f_S(256 BCK Clocks)

5 Packets ´ 32 Bits

LRCK

BCK

DI

CMD

Ch 1

Ch 2

Ch 15

Ch 16

Don’t Care

CMD

DCI

DID = 1

DCO

DCI

2 BCK Delay

14 BCK Delay

DID = 2

DCO

DCI

DID = 8

DCO

Figure 72. DCO Output Timing with Skip Operation

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Command Packet

LRCK

BCK

DI

DID EMD

DCO1

DCO2

Figure 73. DCO Output Timing with Skip Operation (for Command Packet 1)

LRCK

BCK

DI

t_(LB)

t_(BL)

t_(BCY)

t_(DS)

t_(DH)

t_(DOE)

DO

t_(DS)

t_(DH)

DCI

t_(COE)

DCO

Figure 74. AC Timing of Daisy-Chain Signals

Table 16. Timing Characteristics for Figure 74

PARAMETER

MIN

20

0

MAX

UNIT

ns

t_(BCY)

t_(LB)

BCK pulse cycle time

LRCK setup time

LRCK hold time

DI setup time

ns

t_(BL)

3

ns

t_(DS)

t_(DH)

t_(DS)

t_(DH)

t_(DOE)

t_(COE)

0

ns

DI hold time

3

ns

DCI setup time

DCI hold time

DO output delay⁽¹⁾

DCO output delay⁽¹⁾

0

ns

3

ns

8

6

ns

(1) Load capacitance is 10 pF.

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ANALOG OUTPUT

Table 17 and Figure 75 show the relationship between the digital input code and analog output.

Table 17. Analog Output Current and Voltage⁽¹⁾

PARAMETER

I_OUTN (mA)

I_OUTP (mA)

V_OUTN (V)

V_OUTP (V)

V_OUT(V)

800000 (–FS)

–1.5

000000 (BPZ)

7FFFFF (+FS)

–5.5

–3.5

3.5

–5.5

–1.5

–1.23

–2.87

0

–4.51

–1.23

–2.91

2.91

(1) V_OUTN is the output of U1, V_OUTP is the output of U2, and V_OUTis the output of U3 in the measurement circuit of Figure 52.

OUTPUT CURRENT vs INPUT CODE

0

-1

I_OUTN

-2

-3

-4

-5

-6

I_OUTP

80000000 (-FS)

000000 (BPZ)

7FFFFFFF (+FS)

Input Code (Hex)

Figure 75. Relationship Between Digital Input and Analog Output

Submit Documentation Feedback

53

Product Folder Link(s): PCM1795

PACKAGE OPTION ADDENDUM

www.ti.com

18-May-2009

PACKAGING INFORMATION

Orderable Device

PCM1795DB

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

SSOP

DB

28

50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

PCM1795DBR

SSOP

DB

28

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

13-Jul-2009

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0 (mm)

B0 (mm)

K0 (mm)

P1

W

Pin1

Diameter Width

(mm) W1 (mm)

(mm) (mm) Quadrant

PCM1795DBR

SSOP

DB

28

2000

330.0

16.4

8.2

10.5

2.5

12.0

16.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

13-Jul-2009

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SSOP DB 28

SPQ

Length (mm) Width (mm) Height (mm)

346.0 346.0 33.0

PCM1795DBR

2000

Pack Materials-Page 2

MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**)

PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,38

0,22

0,65

28

M

0,15

15

0,25

0,09

5,60

5,00

8,20

7,40

Gage Plane

1

14

0,25

A

0°–ā8°

0,95

0,55

Seating Plane

0,10

2,00 MAX

0,05 MIN

PINS **

14

16

20

24

28

30

38

DIM

6,50

5,90

6,50

5,90

7,50

8,50

7,90

10,50

9,90

10,50 12,90

A MAX

A MIN

6,90

9,90

12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

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