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DSP56301VF100 参数 Datasheet PDF下载

DSP56301VF100图片预览
型号: DSP56301VF100
PDF下载: 下载PDF文件 查看货源
内容描述: 24位数字信号处理器 [24-Bit Digital Signal Processor]
分类和应用: 外围集成电路数字信号处理器时钟
文件页数/大小: 124 页 / 2296 K
品牌: FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
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Signals/Connections
1
The DSP56301 input and output signals are organized into functional groups, as shown in
and illustrated
in
The DSP56301 operates from a 3 V supply; however, some of the inputs can tolerate 5 V. A special
notice for this feature is added to the signal descriptions of those inputs.
Table 1-1.
DSP56301
Functional Signal Groupings
Number of
Signals by
Package Type
TQFP
Power (V
CC
)
1
Ground (GND)
1
Clock
PLL
Address Bus
Port A
Data Bus
Bus Control
Interrupt and Mode Control
Host Interface (HI32)
Enhanced Synchronous Serial Interface (ESSI)
Port B
3
Ports C and D
4
2
Functional Group
Detailed Description
MAP-
BGA
45
38
2
3
24
24
15
5
52
12
and
25
26
2
3
24
24
15
5
52
12
Serial Communication Interface (SCI)
Timer
JTAG/OnCE Port
Notes:
1.
Port E
5
3
3
6
3
3
6
2.
3.
4.
5.
6.
The number of available power and ground signals is package-dependent. In the TQFP package specific pins are dedicated
internally to device subsystems. In the MAP-BGA package, power and ground connections (except those providing PLL
power) connect to internal power and ground planes, respectively.
Port A signals define the external memory interface port, including the external address bus, data bus, and control signals.
Port B signals are the HI32 port signals multiplexed with the GPIO signals.
Port C and D signals are the two ESSI port signals multiplexed with the GPIO signals.
Port E signals are the SCI port signals multiplexed with the GPIO signals.
Each device also includes several no connect (NC) pins. The number of NC connections is package-dependent: the TQFP
has 9 NCs and the MAP-BGA has 20 NCs. Do not connect any line, component, trace, or via to these pins. See
Chapter 3
for details.
DSP56301 Technical Data, Rev. 10
Freescale Semiconductor
1-1