66-MHz Electrical Characteristics
illustrates the power-down sequence if a keep-alive supply is required.
V
DDH
V
DDL
0.5-V Max
3.1-V Max
V
DDKA
Ramp down rates may
differ with load.
V
DDH
cannot lag V
DDL
by more than 3.1 V.
V
DDH
≥
V
DDL
- 0.5 V (V
DDH
cannot lead V
DDL
by more than 0.5 V.)
Figure G-4. Option A Power-Down Sequence With Keep-Alive Supply
G.9.2
Power-Up/Down Option B
A less stringent power-up sequence may be implemented if 2.6-V compliant pins and dual 2.6-V/5-V
compliant pins are NOT connected to the 5-V supply with a pull-up resistor or driven by 5-V logic during
power-up/down.
The option B power-up sequence (excluding V
DDKA
) is:
1. V
DDH
> V
DDL
- 0.5 V (V
DDH
cannot lag V
DDL
by more than 0.5 V)
Thus the V
DDH
supply group can be fully powered-up prior to power-up of the V
DDL
supply group, with
no adverse affects to the device.
The requirement that V
DDH
cannot lag V
DDL
by more than 0.5 V is due to ESD diodes in the pad logic for
dual 2.6-V/5-V compliant pins and 2.6-V pins. The diodes are forward biased when V
DDL
is greater than
V
DDH
and will start to conduct current.
illustrates the power-up sequence if no keep-alive supply is required.
illustrates the
power-up sequence if a keep-alive supply is required. The keep-alive supply should be powered-up at the
same time or before both the high voltage and low voltage supplies are powered-up.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
G-15
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
