HY57V283220(L)T(P) / HY5V22(L)F(P)
PIN CONFIGURATION ( HY57V283220(L)T(P) Series)
V
DD
DQ0
V
DDQ
DQ1
DQ2
V
SSQ
DQ3
DQ4
V
DDQ
DQ5
DQ6
V
SSQ
DQ7
NC
V
DD
DQM0
/W E
/C A S
/R A S
/C S
A11
BA0
BA1
A 1 0 /A P
A0
A1
A2
DQM2
V
DD
NC
D Q 16
V
SSQ
D Q 17
D Q 18
V
DDQ
D Q 19
D Q 20
V
SSQ
D Q 21
D Q 22
V
DDQ
D Q 23
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
V
SS
D Q 15
V
SSQ
D Q 14
D Q 13
V
DDQ
D Q 12
D Q 11
V
SSQ
D Q 10
DQ9
V
DDQ
DQ8
NC
V
SS
DQM1
NC
NC
C LK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
V
SS
NC
D Q 31
V
DDQ
D Q 30
D Q 29
V
SSQ
D Q 28
D Q 27
V
DDQ
D Q 26
D Q 25
V
SSQ
D Q 24
V
SS
8 6 p in T S O P II
4 0 0 m il x 8 7 5 m i l
0 .5 m m p i n p i t c h
PIN DESCRIPTION
PIN
CLK
CKE
CS
BA0, BA1
A0 ~ A11
Clock
Clock Enable
Chip Select
Bank Address
Address
Row Address Strobe,
Column Address Strobe,
Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Data Output Power/Ground
No Connection
PIN NAME
DESCRIPTION
The system clock input. All other inputs are registered to the SDRAM
on the rising edge of CLK.
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
Enables or disables all inputs except CLK, CKE and DQM
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA7
Auto-precharge flag : A10
RAS, CAS and WE define the operation
Refer function truth table for details
Controls output buffers in read mode and masks input data in write mode
Multiplexed data input / output pin
Power supply for internal circuits and input buffers
Power supply for output buffers
No connection
RAS, CAS, WE
DQM0~3
DQ0 ~ DQ31
V
DD
/V
SS
V
DDQ
/V
SSQ
NC
Rev. 0.9 / July 2004
3
HYNIX [ HYNIX SEMICONDUCTOR ]
