ICS9250-27
Frequency Generator and Integrated Buffers for Celeron & PII/III
TM
General Description
The
ICS9250-27
is a single chip clock solution for 810/810E and 815 type chipset. It provides all necessary clock
signals for such a system.
Spread spectrum may be enabled through I
2
C programming. Spread spectrum typically reduces EMI by 8dB to 10
dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9250-
27 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and
temperature variations.
Pin Description
PIN NUMBER
1
3
4
PIN NAME
FS2
REF0
X1
X2
TYPE
IN
OUT
IN
OUT
PWR
OUT
PWR
OUT
OUT
OUT
OUT
IN
I/O
IN
IN
OUT
OUT
OUT
PWR
OUT
DESCRIPTION
Function Select pin. Determines CPU frequency, all output functionality
3.3V, 14.318MHz reference clock output.
Cr ystal input, has inter nal load cap (33pF) and feedback
resistor from X2
Cr ystal output, nominally 14.318MHz. Has inter nal load
cap (33pF)
Ground pins for 3.3V supply
3.3V Fixed 66MHz clock outputs for HUB
3 . 3 V p ow e r s u p p l y
Free r unning 3.3V PCI clock output
3.3V PCI clock outputs
3.3V Fixed 48MHz clock outputs for USB
3.3V fixed 48MHz clock output. Stronger output for graphics/video
interface (minimum 1V/ns edge rate)
Function Select pins. Determines CPU frequency, all output
functionality. Please refer to Functionality table on page 1
Data pin for I
2
C circuitr y 5V tolerant
Clock pin of I
2
C circuitr y 5V tolerant
Asynchronous active low input pin used to power down the device
into a low power state. The inter nal clocks are disabled and the VCO
a n d t h e c r y s t a l a r e s t o p p e d . T h e l a t e n c y o f t h e p ow e r d ow n w i l l n o t
b e g r e a t e r t h a n 3 m s.
3.3V output r unning 100MHz. All SDRAM outputs can be tur ned off
t h r o u g h I
2
C
3 . 3 V f r e e r u n n i n g 1 0 0 M H z S D R A M , c a n n o t b e t u r n e d o f f t h r o u g h I
2
C
2.5V Host bus clock output. 66MHz, 100MHz or 133MHz depending
o n F S p i n s.
2.5V power suypply for CPU & IOAPIC
2 . 5 V c l o ck o u t p u t s r u n n i n g a t 3 3 . 3 M H z .
5, 6, 14, 17, 23,
24, 35, 41, 47, GND
48, 56
9, 8, 7
2, 10, 11, 21,
22, 27, 33, 38,
44
12
20, 19, 18, 16,
15, 13
25
26
29, 28
30
31
32
36, 37, 39, 40,
42, 43, 45, 46
34
49, 50, 52
51, 53
54, 55
3V66 (2:0)
VDD
PCICLK_F
PCICLK (5:0)
48MHz_0
48MHz_1
FS (1:0)
SDATA
SCLK
PD#
SDRAM (7:0)
SDRAM_F
CPUCLK
(2:0)
VDDL
IOAPIC (1:0)
IDT
TM
Frequency Generator and Integrated Buffers for Celeron & PII/III
TM
0395F—01/25/10
2
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
