64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Configuration Registers
Figure 14:
Configuration Register WRITE in Synchronous Mode Followed by READ ARRAY
Operation
CLK
Latch Control Register Value
A[21:0]
(except A19)
A19
2
OPCODE
tHD
tSP
ADDRESS
Latch Control Register Address
ADDRESS
tSP
CRE
tSP
tHD
tHD
tCSP
tCBPH
3
ADV#
CE#
OE#
WE#
LB#/UB#
WAIT
DQ[15:0]
tSP
tHD
tCW
High-Z
High-Z
DATA
VALID
DON’T CARE
Notes: 1. Non-default BCR settings for configuration register WRITE in synchronous mode followed
by READ ARRAY operation: Latency code two (three clocks); WAIT active LOW; WAIT
asserted during delay.
2. A[19] = LOW to load RCR; A[19] = HIGH to load BCR.
3. CE# must remain LOW to complete a burst-of-one WRITE. WAIT must be monitored—addi-
tional WAIT cycles caused by refresh collisions require a corresponding number of addi-
tional CE# LOW cycles.
PDF: 09005aef80be1fbd/Source: 09005aef80be2036
Burst CellularRAM_2.fm - Rev. G 10/05 EN
18
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