64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Configuration Registers
Configuration Registers
Two user-accessible configuration registers define the device operation. The bus config-
uration register (BCR) defines how the CellularRAM interacts with the system memory bus
and is nearly identical to its counterpart on burst mode Flash devices. The refresh configu-
ration register (RCR) is used to control how refresh is performed on the DRAM array.
These registers are automatically loaded with default settings during power-up, and can
be updated any time the devices are operating in a standby state.
Access Using CRE
The configuration registers are loaded using either a synchronous or an asynchronous
WRITE operation when the control register enable (CRE) input is HIGH (see Figure 13
below and Figure 14 on page 18). When CRE is LOW, a READ or WRITE operation will
access the memory array. The register values are placed on addresses A[21:0]. In an asyn-
chronous WRITE, the values are latched into the configuration register on the rising
edge of ADV#, CE#, or WE#, whichever occurs first; LB# and UB# are “Don’t Care.” Access
using CRE is WRITE only. The BCR is accessed when A[19] is HIGH; the RCR is accessed
when A[19] is LOW.
Figure 13:
Configuration Register WRITE in Asynchronous Mode Followed by READ ARRAY
Operation
CLK
A[21:0]
(except A19)
OPCODE
tAVS
Select Control Register
ADDRESS
tAVH
A19
1
CRE
tVPH
tAVS
tAVH
ADDRESS
ADV#
tVP
tCBPH
CE#
Initiate Control Register Access
tCW
OE#
tWP
WE#
LB#/UB#
DQ[15:0]
Write Address Bus Value
to Control Register
DATA VALID
DON’T CARE
Note:
A[19] = LOW to load RCR; A[19] = HIGH to load BCR.
PDF: 09005aef80be1fbd/Source: 09005aef80be2036
Burst CellularRAM_2.fm - Rev. G 10/05 EN
17
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
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