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    PI7C8150AMAE-33 参数 Datasheet PDF下载

    PI7C8150AMAE-33图片预览
    型号： PI7C8150AMAE-33
    PDF下载： 下载PDF文件 查看货源
    内容描述： 双端口PCI至PCI桥接器 [2-PORT PCI-to-PCI BRIDGE]
    分类和应用： 总线控制器微控制器和处理器外围集成电路PC时钟
    文件页数/大小： 111 页 / 1727 K
    品牌： PERICOM [ PERICOM SEMICONDUCTOR CORPORATION ]
     浏览型号PI7C8150AMAE-33的Datasheet PDF文件第4页浏览型号PI7C8150AMAE-33的Datasheet PDF文件第5页浏览型号PI7C8150AMAE-33的Datasheet PDF文件第6页浏览型号PI7C8150AMAE-33的Datasheet PDF文件第7页浏览型号PI7C8150AMAE-33的Datasheet PDF文件第9页浏览型号PI7C8150AMAE-33的Datasheet PDF文件第10页浏览型号PI7C8150AMAE-33的Datasheet PDF文件第11页浏览型号PI7C8150AMAE-33的Datasheet PDF文件第12页  
    PI7C8150A
    2-PORT PCI-TO-PCI BRIDGE
    14.1.33
    4Ch
    14.1.34
    14.1.35
    14.1.36
    14.1.37
    58h
    14.1.38
    14.1.39
    14.1.40
    14.1.41
    14.1.42
    14.1.43
    14.1.44
    14.1.45
    14.1.46
    14.1.47
    14.1.48
    14.1.49
    14.1.50
    14.1.51
    14.1.52
    14.1.53
    14.1.54
    14.1.55
    SECONDARY BUS ARBITER PREEMPTION CONTROL REGISTER – OFFSET
    .......................................................................................................................................... 89
    UPSTREAM (S TO P) MEMORY BASE REGISTER – OFFSET 50h
    ........................ 89
    UPSTREAM (S TO P) MEMORY LIMIT REGISTER – OFFSET 50h.......................
    90
    UPSTREAM (S TO P) MEMORY BASE UPPER 32-BITS REGISTER – OFFSET 54h
    .......................................................................................................................................... 90
    UPSTREAM (S TO P) MEMORY LIMIT UPPER 32-BITS REGISTER – OFFSET
    .......................................................................................................................................... 90
    P_SERR_L EVENT DISABLE REGISTER – OFFSET 64h........................................
    90
    GPIO DATA AND CONTROL REGISTER – OFFSET 64h
    ........................................ 91
    SECONDARY CLOCK CONTROL REGISTER – OFFSET 68h
    ................................. 92
    P_SERR_L STATUS REGISTER – OFFSET 68h
    ........................................................ 92
    PORT OPTION REGISTER – OFFSET 74h
    ................................................................ 93
    RETRY COUNTER REGISTER – OFFSET 78h
    .......................................................... 95
    PRIMARY MASTER TIMEOUT COUNTER – OFFSET 80h
    ..................................... 95
    SECONDARY MASTER TIMEOUT COUNTER – OFFSET 80h
    ............................... 95
    CAPABILITY ID REGISTER – OFFSET B0h
    ............................................................. 95
    NEXT POINTER REGISTER – OFFSET B0h
    ............................................................. 95
    SLOT NUMBER REGISTER – OFFSET B0h
    .............................................................. 96
    CHASSIS NUMBER REGISTER – OFFSET B0h
    ....................................................... 96
    CAPABILITY ID REGISTER – OFFSET DCh.............................................................
    96
    NEXT ITEM POINTER REGISTER – OFFSET DCh
    ................................................. 96
    POWER MANAGEMENT CAPABILITIES REGISTER – OFFSET DCh
    ................. 96
    POWER MANAGEMENT DATA REGISTER – OFFSET E0h...................................
    97
    CAPABILITY ID REGISTER – OFFSET E4h
    ............................................................. 97
    NEXT POINTER REGISTER – OFFSET E4h
    ............................................................. 97
    15
    BRIDGE BEHAVIOR .......................................................................................... 97
    15.1
    BRIDGE ACTIONS FOR VARIOUS CYCLE TYPES........................................................... 98
    15.2
    ABNORMAL TERMINATION (INITIATED BY BRIDGE MASTER)................................ 98
    15.2.1 MASTER ABORT................................................................................................................
    98
    15.2.2 PARITY AND ERROR REPORTING
    ................................................................................ 98
    15.2.3 REPORTING PARITY ERRORS
    ....................................................................................... 99
    15.2.4 SECONDARY IDSEL MAPPING
    ...................................................................................... 99
    16
    IEEE 1149.1 COMPATIBLE JTAG CONTROLLER ..................................... 99
    BOUNDARY SCAN ARCHITECTURE................................................................................. 99
    TAP PINS
    .......................................................................................................................... 100
    INSTRUCTION REGISTER
    ............................................................................................ 100
    BOUNDARY SCAN INSTRUCTION SET .......................................................................... 101
    TAP TEST DATA REGISTERS............................................................................................ 102
    BYPASS REGISTER ............................................................................................................. 102
    BOUNDARY-SCAN REGISTER.......................................................................................... 102
    TAP CONTROLLER ............................................................................................................. 102
    16.1
    16.1.1
    16.1.2
    16.2
    16.3
    16.4
    16.5
    16.6
    17
    17.1
    17.2
    17.3
    17.4
    17.5
    17.6
    ELECTRICAL AND TIMING SPECIFICATIONS....................................... 106
    MAXIMUM RATINGS ......................................................................................................... 106
    DC SPECIFICATIONS .......................................................................................................... 106
    AC SPECIFICATIONS.............................................................................................................. 107
    66MHZ TIMING.................................................................................................................... 108
    33MHZ TIMING.................................................................................................................... 108
    POWER CONSUMPTION .................................................................................................... 108
    Page 8 of 111
    APRIL 2006 – Revision 1.1
    06-0057

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