K6X8016T3B Family
AC OPERATING CONDITIONS
TEST CONDITIONS
(Test Load and Input/Output Reference)
Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
Input and output reference voltage:1.5V
Output load(see right): C
L
=100pF+1TTL
C
L
=50pF+1TTL
CMOS SRAM
C
L
1
)
1.Including scope and jig capacitance
AC CHARACTERISTICS
(V
CC
=2.7~3.6V, Industrial product:T
A
=-40 to 85°C, Automotive product:T
A
=-40 to 125°C)
Speed Bins
Parameter List
Symbol
Min
Read cycle time
Address access time
Chip select to output
Output enable to valid output
Chip select to low-Z output
Read
Output enable to low-Z output
LB, UB enable to low-Z output
Chip disable to high-Z output
Output Disable to High-Z Output
Output hold from address change
LB, UB valid to data output
UB, LB disable to high-Z output
Write cycle time
Chip select to end of write
Address set-up time
Address valid to end of write
Write pulse width
Write
Write recovery time
Write to output high-Z
Data to write time overlap
Data hold from write time
End write to output low-Z
LB, UB valid to end of write
1. Voltage range is 3.0V~3.6V for industrial product.
55ns
1
)
Max
-
55
55
25
-
-
-
20
20
-
25
20
-
-
-
-
-
-
20
-
-
-
-
Min
70
-
-
-
10
5
5
0
0
10
-
0
70
60
0
60
55
0
0
30
0
5
60
70ns
Max
-
70
70
35
-
-
-
25
25
-
35
25
-
-
-
-
-
-
25
-
-
-
-
Units
t
RC
t
AA
t
CO
t
OE
t
LZ
t
OLZ
t
BLZ
t
HZ
t
OHZ
t
OH
t
BA
t
BHZ
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
t
BW
55
-
-
-
10
5
5
0
0
10
-
0
55
45
0
45
40
0
0
20
0
5
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DATA RETENTION CHARACTERISTICS
Item
Vcc for data retention
Data retention current
Data retention set-up time
Recovery time
Symbol
V
DR
I
DR
t
SDR
t
RDR
CS≥Vcc-0.2V
Vcc=1.5V, CS≥Vcc-0.2V
K6X8016T3B-F
K6X8016T3B-Q
See data retention waveform
Test Condition
Min
1.5
-
-
0
5
Typ
-
-
-
-
-
Max
3.6
6
10
-
-
ms
Unit
V
µA
5
Revision 1.0
September 2003
SAMSUNG [ SAMSUNG SEMICONDUCTOR ]
