K6X8016T3B Family
TIMING DIAGRAMS
CMOS SRAM
TIMING WAVEFORM OF READ CYCLE(1)
(Address Controlled
,
CS=OE=V
IL
, WE=V
IH
, UB or/and LB=V
IL
)
t
RC
Address
t
OH
Data Out
Previous Data Valid
t
AA
Data Valid
TIMING WAVEFORM OF READ CYCLE(2)
(WE=V
IH
)
t
RC
Address
t
AA
t
CO
t
OH
CS
t
HZ
UB, LB
t
BA
t
BHZ
OE
t
OLZ
t
BLZ
Data out
High-Z
t
OE
t
OHZ
Data Valid
t
LZ
NOTES
(READ CYCLE)
1.
t
HZ
and
t
OHZ
are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition,
t
HZ
(Max.) is less than
t
LZ
(Min.) both for a given device and from device to device
interconnection.
6
Revision 1.0
September 2003