D a t a S h e e t ( P r e l i m i n a r y )
9.7
Write Status Register (WRSR)
The Write Status Register (WRSR) command changes the bits in the Status Register. A Write Enable
(WREN) command, which itself sets the Write Enable Latch (WEL) in the Status Register, is required prior to
writing the WRSR command. Table 9.2, S25FL032A Status Register on page 18 shows the status register
bits and their functions.
The host system must drive CS# low, write the WRSR command, and the appropriate data byte on SI
(Figure 9.7).
The WRSR command cannot change the state of the Write Enable Latch (bit 1). The WREN command must
be used for that purpose. Bit 0 is a status bit controlled internally by the Flash device. Bits 6 and 5 are always
read as 0 and have no user significance.
The WRSR command also controls the value of the Status Register Write Disable (SRWD) bit. The SRWD bit
and W# together place the device in the Hardware Protected Mode (HPM). The device ignores all WRSR
commands once it enters the Hardware Protected Mode (HPM). Table 9.3 shows that W# must be driven low
and the SRWD bit must be 1 for this to occur.
Figure 9.7 Write Status Register (WRSR) Command Sequence
CS#
8
9
10
12 13 14 15
11
4
6
7
Mode 3
0
1
2
3
5
SCK
Mode 0
Command
Register In
Status
7
6
5
4
3
2
1
0
SI
MSB
Hi-Z
SO
Table 9.3 Protection Modes
Protected Area
(See Note)
Unprotected Area
(See Note)
W# Signal
SRWD Bit
Mode
Write Protection of the Status Register
1
1
0
1
0
0
Status Register is writable (if the WREN
command has set the WEL bit). The values in
the SRWD, BP2, BP1 and BP0 bits can be
changed.
Software
Protected
(SPM)
Ready to accept Page
Program and Sector Erase
commands
Protected against program
and erase commands
Hardware
Protected
(HPM)
Status Register is Hardware write protected.
The values in the SRWD, BP2, BP1 and BP0
bits cannot be changed.
Ready to accept Page
Program and Sector Erase
commands
Protected against program
and erase commands
0
1
Note
As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in Table 7.1 on page 11.
Table 9.3 shows that neither W# or SRWD bit by themselves can enable HPM. The device can enter HPM
either by setting the SRWD bit after driving W# low, or by driving W# low after setting the SRWD bit.
However, the device disables HPM only when W# is driven high.
Note that HPM only protects against changes to the status register. Since BP2:BP0 cannot be changed in
HPM, the size of the protected area of the memory array cannot be changed. Note that HPM provides no
protection to the memory array area outside that specified by BP2:BP0 (Software Protected Mode, or SPM).
If W# is permanently tied high, HPM can never be activated, and only the SPM (BP2:BP0 bits of the Status
Register) can be used.
20
S25FL032A
S25FL032A_00_C0 September 1, 2006
SPANSION [ SPANSION ]
