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S25FL032A0LMFI001 参数 Datasheet PDF下载

S25FL032A0LMFI001图片预览
型号: S25FL032A0LMFI001
PDF下载: 下载PDF文件 查看货源
内容描述: 32兆位CMOS 3.0伏闪存与50MHz的SPI (串行外设接口)总线 [32 Megabit CMOS 3.0 Volt Flash Memory with 50MHz SPI (Serial Peripheral Interface) Bus]
分类和应用: 闪存
文件页数/大小: 36 页 / 944 K
品牌: SPANSION [ SPANSION ]
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Da ta
Shee t
(Prelimi nar y)
9.8
Page Program (PP)
The Page Program (PP) command changes specified bytes in the memory array (from 1 to 0 only). A WREN
command is required prior to writing the PP command.
The host system must drive CS# low, and then write the PP command, three address bytes, and at least one
data byte on SI. CS# must be driven low for the entire duration of the PP sequence. The command sequence
is shown in
and
The device programs only the last 256 data bytes sent to the device. If the number of data bytes exceeds this
limit, the bytes sent before the last 256 bytes are discarded, and the device begins programming the last 256
bytes sent at the starting address of the specified page. This may result in data being programmed into
different addresses within the same page than expected. If fewer than 256 data bytes are sent to device, they
are correctly programmed at the requested addresses.
The host system must drive CS# high after the device has latched the 8th bit of the data byte, otherwise the
device does not execute the PP command. The PP operation begins as soon as CS# is driven high. The
device internally controls the timing of the operation, which requires a period of t
PP
. The Status Register may
be read to check the value of the Write In Progress (WIP) bit while the PP operation is in progress. The WIP
bit is 1 during the PP operation, and is 0 when the operation is completed. The device internally resets the
Write Enable Latch to 0 before the operation completes (the exact timing is not specified).
The device does not execute a Page Program (PP) command that specifies a page that is protected by the
Block Protect bits (BP2:BP0) (see
Figure 9.8
Page Program (PP) Command Sequence
CS#
Mode
3
0
1
2
3
4
5
6
7
8
9 10
28 29
30 31 32 33 34 35 36 37 38
39
SCK
Mode 0
Command
24-Bit Address
23 22 21
MSB
3
2
1
0
7
6
5
Data Byte 1
4
3
2
1
0
SI
MSB
2072
2074
2075
2073
2076
CS#
40 41 42 43 44 45 46 47 48 49 50
51 52 53 54
55
2077
2078
1
0
SCK
Data Byte 2
Data Byte
3
1
0
7
6
5
4
3
2
1
0
7
MSB
6
Data Byte 256
5
4
3
2
SI
7
MSB
6
5
4
3
2
MSB
September 1, 2006 S25FL032A_00_C0
S25FL032A
2079
21