tm
TE
CH
T2316405A
Preliminary T2316407A
11. tWCS, tRWD, tAWD and tCWD are
restrictive operating parameters in LATE
WRITE and READ-MODIFY -WRITE cycles
only. If t CS
≥
tWCS(min), the cycle is an
W
EARLY WRITE cycle and the data output will
remain an open circuit throughout the entire
cycle. If tRWD
≥
tRWD(min), tAWD
≥
tAWD (min) and tCWD
≥
tCWD(min), the
cycle is READ-WRITE and the data output
will contain data read from the selected cell. If
neither of the above conditions is met, the state
of I/O (at access time and until CAS and
RAS
or
OE
go back to VIH) is indeterminate.
OE held high and WE taken low after CAS
goes low result in a LATE WRITE ( OE -
controlled) cycle.
12. These parameters are referenced to CAS
leading edge in EARLY W
RITE cycles and
WE
leading edge in LATE WRITE or READ-
MODIFY-WRITE cycles.
13. During a READ cycle, if
OE
is low then taken
HIGH before CAS goes high, I/O goes open,
if OE is tied permanently low, a LATE
WRITE
or
READ-MODIFY-WRITE
operation is not possible.
14. WRITE command is defined as WE going low.
15. LATE WRITE and READ-MODIFY-WRITE
cycles must have both tOFF2 and tOEH met
(
OE
high during WRITE cycle) in order to
ensure that the output buffers will be open
during the WRITE cycles.
16. The I/Os open during READ cycles once
tOFF1 or tOFF2 occur.
Notes:
1. An initial pause of 200us is required after
power-up followed by eight RAS refresh
cycles ( RAS only or CBR) before proper
device operation is assured. The eight
RAS
cycle wake -ups should be repeated any time
the tREF refresh requirement is exceeded.
2. V IH(2.0V) and VIL(0.8V) are reference
levels for measuring timing of input signals.
Transition times are measured between
V IH(2.0V) and VIL(0.8V).
3. In addition to meet the transition rate
specification, all input signals must transit
between VIH and VIL in a monotonic manner.
4. Assume that tRCD < tRCD(max). If tRCD is
greater than the maximum recommended value
shown in this table, tRAC will increase by the
amount that t RCD exceeds the value shown.
5. Assume that tRCD
≥
tRCD(max) .
6. Enables on-chip refresh and address counters.
7. Operation within the tRCD(max) limit ensures
that tRAC(max) can be met. tRCD(max) is
specified as a reference point only; if tRCD is
greater than the specified tRCD(max) limit,
access time is controlled by tCAC.
8. Operation within the tRAD limit ensures that
tRAC(max) can be met. tRAD(max) is
specified as a reference point only; if tRAD is
greater than the specified t AD(max) limit,
R
access time is controlled by tAA.
9. Either tRCH or tRRH must be satisfied for a
READ cycle.
10. tOFF1 (max) defines the time at which the
output achieves the open circuit condition; it is
not a reference to VOH or VOL .
Taiwan Memory Technology, Inc. reserves the right
P. 7
to change products or specifications without notice.
Publication Date: APR. 2001
Revision:0.B
TMT [ TAIWAN MEMORY TECHNOLOGY ]
