tm
TE
CH
READ CYCLE
tR C
tRAS
T2316405A
Preliminary T2316407A
tRP
RA S V IH
V IL
t C SH
t R SH
tC R P
tR C D
tCAS
tRRH
CA S
V IH
V IL
tR A D
tA S R
tRAH
RO W
tA R
t R AL
tA S C
tCAH
ROW
t RC H
A DDR
V IH
V IL
CO LUMN
tR C S
WE V IH
V IL
tA A
t R AC
t C AC
tCLZ
N OTE 1
tO F F 1
V
I/O V OH
OL
V IH
V IL
OP EN
tO A C
V A L ID D A T A
tO F F 2
O PE N
OE
EARLY WRITE CYCLE
tR C
tR A S
RAS
V IH
V IL
tR P
tC R P
V
C AS V IH
IL
tR A D
tR A H
ROW
t RC D
tC S H
tR S H
tCAS
tA R
tA S R
tA S C
tRAL
tCAH
ROW
A DDR
V IH
V IL
CO LUMN
tC W L
tR W L
t WC S
tW C R
tW P
tW C H
WE
V IH
V IL
t DS
tD H R
tD H
V A L ID D A T A
V
I/O V IOH
IOL
OE
V IH
V IL
DON'T CARE
UNDEFINED
Note:
t
OFF1
is referenced from the rising edge of
RAS
or
CAS
, whichever occurs last.
2
Taiwan Memory Technology, Inc. reserves the right
P. 8
to change products or specifications without notice.
Publication Date: APR. 2001
Revision:0.B
TMT [ TAIWAN MEMORY TECHNOLOGY ]
