Core1553BRT-EBR Enhanced Bit Rate 1553 Remote Terminal
Core1553BRT-EBR Device
Requirements
The Core1553BRT-EBR can be implemented in several
Actel FPGA devices.
gives the utilization and
performance figures for the core implemented in these
devices.
The core can operate with a clock of up to 24 MHz. This
clock rate is easily met in all Actel silicon families noted
in
The FSM_ERROR output can be left unconnected if the
system is not required to detect and report state
machines entering illegal states.
Enhanced Bit Rate 1553 Bus
Overview
Enhanced Bit Rate 1553 is a enhanced data rate
MIL-STD-1553B bus. The data transmission rate has been
increased from 1 MB/Sec to 10 MB/Sec, and the multi-
drop bus structure has been replaced with a hub-based
point-to-point bus structure. To maintain system
compatibility, the data protocol and command, status,
and data words are identical to the MIL-STD-1553B
specification.
The bus has a single active bus controller (BC) and up to
31 remote terminals (RTs). For 1553EBR, the BC has up to
31 separate transceivers, each one connected directly to
an RT. The BC manages all data transfers on the bus using
the command and status protocol. The bus controller
initiates every transfer by sending a command word and
data if required. The selected RT will respond with a
status word and data if required.
The 1553EBR command word contains a five-bit RT
address, transmit or receive bit, five-bit sub-address, and
five-bit word count. This allows for 32 RTs on the bus.
However, since RT address 31 is used to indicate a
broadcast transfer, only 31 RTs may be connected. Each
RT has 30 sub-addresses reserved for data transfers. The
other two sub-addresses (0 and 31) are reserved for
mode codes used for bus control functions. Data
transfers contain up to 32 16-bit data words. Mode code
command words are used for bus control functions, such
as synchronization.
Core1553BRT-EBR Verification
and Compliance
The Core1553BRT-EBR functionality has been verified in
simulation and hardware.
To fully verify compliance, the core has been
implemented on AX1000 and ProASIC3 parts connected
to external transceivers and memory.
Core1553BRT-EBR Fail-Safe State
Machines
The logic design of Core1553BRT-EBR implements fail-
safe state machines. All state machines include illegal
state detection logic. If a state machine should ever enter
an illegal state, the core will assert its FSM_ERROR
output and the state machine will reset. If this occurs,
Actel recommends that the external system reset the
core and also assert the TFLAG input to inform the bus
controller that a serious error has occurred within the
remote terminal.
Table 1 •
Device Utilization
Family
ProASIC3/E
ProASIC
PLUS
Axcelerator
RTAX-S
Comb.
970
1298
658
658
Seq.
467
467
463
463
Total
1437
1765
1121
1121
Device
A3P250
APA150
AX500
RTAX250S
Utilization
24%
29%
14%
27%
Performance
115/55 MHz
105/55 MHz
173/87 MHz
126/62 MHz
Note:
The Performance column shows the maximum clock speed for the 100 MHz and 50 MHz clock domains for each FPGA family.
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A d v a n c e d v 1 .1
ACTEL [ Actel Corporation ]
