Core1553BRT-EBR Enhanced Bit Rate 1553 Remote Terminal
The core consists of six main blocks: 1553EBR encoders, 1553EBR decoders, backend interface, command decoder, RT
controller blocks, and a command legalization block (see
Encoder
BusA
RT Protocol
Controller
Backend
Interface
Memory
2048×16
Decoder
BusB
Decoder
Command
Decoder
Command
Legalization
Core1553BRT-EBR
Figure 2 •
Core1553BRT-EBR RT Block Diagram
In the Core1553BRT-EBR, a single 1553EBR encoder is
used. This takes each word to be transmitted and
serializes it, after which the signal is Manchester
encoded. The encoder also includes both logic to prevent
the RT from transmitting for greater than the allowed
period and loopback fail logic. The loopback logic
monitors the received data and verifies that the core has
correctly received every word that it transmits.
The output of the encoder is gated with the bus enable
signals to select which buses the RT should use to
transmit.
The core includes two 1553EBR decoders. The decoder
takes the serial Manchester data received from the bus
and extracts the received data words. The decoder
requires a 100 MHz clock to extract the data and the
clock from the serial stream.
The decoder contains a digital phased-lock loop (PLL)
that generates a recovery clock used to sample the
incoming serial data. The data is then deserialized and
the 16-bit word decoded. The decoder detects whether a
command or data word is received, and also performs
Manchester encoding and parity error checking.
The backend interface for the Core1553BRT-EBR allows a
simple connection to a memory device or direct
connection to other devices, such as analog-to-digital
converters. The access rates to this memory are slow,
with one read or write every 2 µs. The backend interface
operates off the internally derived 50 MHz clock,
resulting in a read or write every 100 clock cycles.
The backend interface can be configured to connect to
either synchronous or asynchronous memory devices. This
allows the core to be connected to synchronous logic,
memory within the FPGA, or external asynchronous
memory blocks.
The core implements a simple sub-address to the memory
address mapping function, allowing the core to be directly
connected to a memory block. The core also supports an
address mapping function that allows the backend
memory map to be modified to emulate legacy 1553EBR
remote terminals, therefore minimizing system and
software changes when adopting the Core1553BRT-EBR.
Associated with this function is the ability to create a user-
specific interrupt vector.
The backend interface supports a standard bus request
and grant protocol, and provides a WAIT input to allow
the core to interface to slow memory devices.
The command decoder and RT controller blocks decode
the incoming command words, verifying their legality.
The protocol state machine then responds to the
command, transmitting or receiving data or processing a
mode code.
The Core1553BRT-EBR has an internal command legality
block that verifies every 1553EBR command word. A
separate interface is provided that, when enabled,
allows the command legality decoder to be implemented
outside the Core1553BRT-EBR. This external interface is
intended for use with netlist versions of the core. For the
RTL version of the core, this interface can be used or the
source code can be modified easily to implement this
function.
A d v an c ed v1 . 1
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ACTEL [ Actel Corporation ]
