bq3285LF
A low input on EXTRAM during the falling
e d g e o f A S lat che s t he addre s s int o
standard bank address latch. A high input
on the EXTRAM input during the falling
edge of AS latches the address into the
extended bank address latch. The contents
of the address latches are copied into the
standard bank index and the extended bank
index registers respectively. EXTRAM is not
latched.
DS
Data strobe input
When MOT = V
CC
, DS controls data trans-
fer during a bq3285LF bus cycle. During a
read cycle, the bq3285LF drives the bus af-
ter the rising edge on DS. During a write
cycle, the falling edge on DS is used to latch
write data into the chip.
When MOT = V
SS
, the DS input is provided
a signal similar to RD, MEMR, or I/OR in
an Intel-based system. The falling edge on
DS is used to enable the outputs during a
read cycle.
The state of the EXTRAM input selects the
address latch used during data access. A
low input on EXTRAM selects the standard
bank latch and the location in the standard
bank pointed to by the value in this latch. A
high input on the EXTRAM selects the ex-
tended bank latch and the location in the
extended bank pointed to by the value in
this latch.
R/W
Read/write input
When MOT = V
CC
, the level on R/W identi-
fies the direction of data transfer. A high
level on R/W indicates a read bus cycle,
whereas a low on this pin indicates a write
bus cycle.
When MOT = V
SS
, R/W is provided a signal
similar to WR, MEMW, or I/OW in an Intel-
based system. The rising edge on R/W
latches data into the bq3285LF.
CS
Chip select input
CS should be driven low and held stable
during the data-transfer phase of a bus cy-
cle accessing the bq3285LF.
INT
Interrupt request output
INT is an open-drain output. This allows
alarm INT to be valid in battery-backup
mode. To use this feature, connect INT
through a resistor to a power supply other
than V
CC
. INT is asserted low when any
event flag is set and the corresponding event
enable bit is also set. INT becomes
high-impedance whenever register C is read
(see the Control/Status Registers section).
32K
32.768 kHz output
32K provides a buffered 32.768 kHz output.
The frequency remains on and fixed at
32.768kHz as long as V
CC
is valid.
EXTRAM
Extended RAM enable
Enables 128 bytes of additional nonvolatile
SRAM. It is connected internally to a 30kΩ
pull-down resistor. To access the RTC reg-
isters, EXTRAM must be low.
The input on this pin also selects the latch
to be used in the data transfer. A low value
selects the standard bank latch. A high
value selects the extended the bank latch.
EXTRAM should be valid for complete ad-
dress, read or write cycle.
RCL
RAM clear input
A low level on the RCL pin causes the con-
tents of each of the 240 storage bytes to be
set to FF(hex). RCL clears the shadow in-
dex registers to 00(hex). The contents of the
clock and control registers are unaffected.
This pin should be used as a user-interface
input (pushbutton to ground) and not con-
nected to the output of any active compo-
nent. RCL input is only recognized when
held low for at least 125ms in the presence
of V
CC
. Using RAM clear does not affect the
battery load. This pin is connected inter-
nally to a 30kΩ pull-up resistor.
BC
3V backup cell input
BC should be connected to a 3V backup cell
for RTC operation and storage register
nonvolatility in the absence of system power.
When V
CC
slews down past V
BC
(3V typical),
the integral control circuitry switches the
power source to BC. When V
CC
returns above
V
BC
, the power source is switched to V
CC
.
On power-up, a voltage within the V
BC
range must be present on the BC pin for
the oscillator to start up.
3
TI [ TEXAS INSTRUMENTS ]
