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EL7532

®

Data Sheet

August 12, 2005

FN7435.5

Monolithic 2A Step-Down Regulator

Features

• 2A continuous current (from -40°C to +85°C)

The EL7532 is a synchronous, integrated FET 2A step-down

regulator with internal compensation. It operates with an

input voltage range from 2.5V to 5.5V, which accommodates

supplies of 3.3V, 5V, or a single Li-Ion battery source. The

2

• Less than 0.18 in footprint for the complete 2A converter

• Max height 1.1mm MSOP10

output can be externally set from 0.8V to V with a resistive

IN

• 1.5MHz (typ.) switching frequency

• 100ms Power-On-Reset output (POR)

• Internally-compensated voltage mode controller

• Up to 94% efficiency

divider.

The EL7532 features PWM mode control. The operating

frequency is typically 1.5MHz. Additional features include a

100ms Power-On-Reset output, <1µA shut-down current,

short-circuit protection, and over-temperature protection.

• <1µA shut-down current

The EL7532 is available in the 10-pin MSOP package,

making the entire converter occupy less than 0.18 in of

PCB area with components on one side only. The package is

specified for operation over the full -40°C to +85°C

temperature range.

• Overcurrent and over temperature protection

• Pb-Free plus anneal available (RoHS compliant)

2

Applications

• PDA and pocket PC computers

Ordering Information

• Bar code readers

PART NUMBER

TAPE &

REEL

PKG.

• ADSL Modems

(BRAND)

PACKAGE

DWG. #

• Portable instruments

• Li-Ion battery powered devices

• ASIC/FPGA/DSP supplies

• Set Top Boxes

EL7532IY

10-Pin MSOP

-

MDP0043

(BABAA)

EL7532IY-T7

(BABAA)

10-Pin MSOP

7”

EL7532IY-T13

(BABAA)

13”

-

Typical Application Schematic

EL7532IYZ

(BAARA) (Note)

10-Pin MSOP

(Pb-free)

EL7532IYZ-T7

(BAARA) (Note)

10-Pin MSOP

(Pb-free)

7”

V

(2.5V-6V)

V

(1.8V@ 2A)

IN

O

VIN

VO

LX

R

3

C

1

100Ω

EL7532IYZ-T13

(BAARA) (Note)

10-Pin MSOP

(Pb-free)

13”

10µF

L

1

VDD

C

2

10µF

1.8µH

C

0.1µF

3

EL7532

NOTE: Intersil Pb-free plus anneal products employ special Pb-free

material sets; molding compounds/die attach materials and 100%

matte tin plate termination finish, which are RoHS compliant and

compatible with both SnPb and Pb-free soldering operations. Intersil

Pb-free products are MSL classified at Pb-free peak reflow

temperatures that meet or exceed the Pb-free requirements of

IPC/JEDEC J STD-020.

FB

R *

EN

2

124kΩ

SGND

PGND

POR

RSI

R *

100kΩ

1

* V = 0.8V * (1 + R / R )

O

2

1

Pinout

SGND

PGND

LX

FB

VO

1

2

3

4

5

10

9

POR

EN

8

VIN

7

6

VDD

RSI

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

1

All other trademarks mentioned are the property of their respective owners.

EL7532

Absolute Maximum Ratings (T = 25°C)

Thermal Information

Thermal Resistance (Typical)

MSOP10 Package (Note 1) . . . . . . . . . . . . . . . . . . .

Operating Ambient Temperature . . . . . . . . . . . . . . . .-40°C to +85°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C

A

V

, V , POR to SGND. . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V

θ

(°C/W)

115

IN DD

JA

LX to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (V + +0.3V)

IN

RSI, EN, V , FB to SGND. . . . . . . . . . . . . . . -0.3V to (V + +0.3V)

O

PGND to SGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V

Peak Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4A

ESD Classification

Human Body Model (Per JESD22-A114-B) . . . . . . . . . . . . Class 2

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are

at the specified temperature and are pulsed tests, therefore: T = T = T

A

J

C

NOTE:

1. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

JA

Tech Brief TB379.

Electrical Specifications

V

= V = V

IN

= 3.3V, C1 = C2 = 10µF, L = 1.8µH, V = 1.8V, unless otherwise specified.

EN O

DD

PARAMETER

DESCRIPTION

CONDITIONS

MIN

TYP

MAX

UNIT

DC CHARACTERISTICS

V

Feedback Input Voltage

790

800

810

250

5.5

2.2

2.4

500

1

mV

nA

V

FB

I

Feedback Input Current

Input Voltage

FB

V

, V

2.5

2

IN DD

IN,OFF

IN,ON

Minimum Voltage for Shutdown

Maximum Voltage for Startup

Supply Current

V

falling

rising

V

IN

2.2

V

I

PWM, V = V

IN DD

= 5V

400

0.1

52

µA

mΩ

A

DD

EN = 0, V = V

IN

DD

R

PMOS FET Resistance

NMOS FET Resistance

Current Limit (GBD)

V

= 5V, wafer test only

80

DS(ON)-PMOS

DS(ON)-NMOS

LMAX

DD

V

35

65

I

3

T

Over-temperature Threshold (GBD)

Over-temperature Hysteresis (GBD)

EN, RSI Current

T rising

T falling

145

130

°C

V

OT,OFF

OT,ON

T

I

, I

EN RSI

V

, V

EN RSI

= 0V and 3.3V

-1

0.8

86

1

V

, V

EN1 RSI1

EN, RSI Rising Threshold

EN, RSI Falling Threshold

= 3.3V

rising

2.4

V

DD

, V

V

EN2 RSI2

Minimum V for POR, WRT Targeted

FB

95

70

%

POR

FB

V

Value

FB

falling

%

FB

V

POR Voltage Drop

I

= 5mA

35

0.1

0.5

mV

%/V

%

OLPOR

SINK

Line Regulation (GBD)

Load Regulation (GBD)

V

= 2.5V to 6V, I

= 2A, V

= 1.8V

LINEREG

LOADREG

IN

OUT

= 0 to 2A

OUT

= 3.3V, V

= 1.8V, I

OUT

AC CHARACTERISTICS

F

PWM Switching Frequency

Minimum RSI Pulse Width (GBD)

Soft-start Time (GBD)

1.35

80

1.5

25

1.65

50

MHz

ns

PWM

t

Guaranteed by design

RSI

650

100

µs

SS

Power On Reset Delay Time (GBD)

120

ms

POR

GBD = Guaranteed By Design

FN7435.5

2

August 12, 2005

EL7532

Pin Descriptions

PIN NUMBER

PIN NAME

PIN FUNCTION

1

2

SGND

PGND

LX

Negative supply for the controller stage

Negative supply for the power stage

3

Inductor drive pin; high current digital output with average voltage equal to the regulator output voltage

Positive supply for the power stage

4

VIN

5

VDD

RSI

Power supply for the controller stage

6

Resets POR timer; Connect to ground if not used

Enable; Can be connected directly to the VIN for enable

Power on reset open drain output; Leave open if not used

Output voltage sense pin

7

EN

8

POR

VO

9

10

FB

Voltage feedback input; connected to an external resistor divider between V and SGND for variable

O

output

Block Diagram

5

V

DD

V

O

9

+

-

4

10pF

V

IN

124K

CURRENT

LIMIT

FB

5M

10

-

+

PWM

COMPEN-

SATION

+

-

PWM

COMPARATOR

P-DRIVER

100K

1.8µ

LX

CONTROL

LOGIC

RAMP

GENERATOR

CLOCK

1.5MHz

1.8V

2A

3

EN

7

EN

SOFT-

START

10µF

N-DRIVER

UNDER-

VOLTAGE

LOCKOUT

+

–

PGND

POR

2

BANDGAP

REFERENCE

100K

PG

2.5V-

5V

TEMPERATURE

SENSE

1

6

SGND

RSI

8

POR

FN7435.5

3

August 12, 2005

EL7532

Typical Performance Curves

100

80

100

80

60

40

20

0

60

V

=1.2V

V

O

=3.3V

O

V

=1.8V

O

V

=2.5V

O

40

20

0

V

=1.2V

O

V

=1.8V

MAXIMUM EFFICIENCY, η=95%

0.5 1.5

(A)

MAXIMUM EFFICIENCY, η=95%

0

1

2

2.5

0

0.5

1

1.5

2

2.5

I

(A)

OUT

FIGURE 1. EFFICIENCY vs I

@ V =5V

IN

FIGURE 2. EFFICIENCY vs I

@ V =3.3V

IN

OUT

100

80

1

I

=2A

O

V

=0.8V

0.6

0.2

-0.2

-0.6

-1

O

60

V

=1.8V

O

V

=2.5V

O

40

V

=1.2V

O

V

4

=3.3V

O

20

MAXIMUM EFFICIENCY, η=94%

0

0.5

1

1.5

2

2.5

3

3.5

4.5

(V)

5

5.5

6

I

(A)

V

IN

OUT

FIGURE 3. EFFICIENCY vs I

@ V =2.5V

IN

FIGURE 4. LINE REGULATION

OUT

1

0.6

0.2

-0.2

-0.6

-1

0.6

V

=0.8V

=3.3V

O

0.2

-0.2

-0.6

-1

V

=0.8V

=2.5V

O

0

0.5

1

1.5

2

0

0.5

1

1.5

(A)

2

2.5

I

(A)

I

OUT

FIGURE 5. LOAD REGULATION @ V =5V

IN

FIGURE 6. LOAD REGULATION @ V =3.3V

IN

FN7435.5

August 12, 2005

4

EL7532

Typical Performance Curves (Continued)

1

∆V

100mV/d

0.5A/d

IN

V

=0.8V

O

0.5

0

i

L

=1.8V

V

2V/d

LX

-0.5

-1

∆V

10mV/d

O

0

0.5

1

1.5

(A)

2

2.5

1µs/d

I

OUT

FIGURE 7. LOAD REGULATION @ V =2.5V

IN

FIGURE 8. LOAD REGULATION @ V =2.5V

IN

V

IN

(1V/d)

(2V/d)

V

O

I

(2V/d)

IN

(0.5A/d)

POR

(2V/d)

V

O

(1V/d)

50ms/d

0.5ms/d

FIGURE 9. START-UP 1

FIGURE 10. START-UP 2

V

IN

(2V/d)

∆V

O

50mV/d

V

O

(2V/d)

2A

RSI

(2V/d)

I

O

POR

(2V/d)

0.1A

50ms/d

0.5ms/d

FIGURE 11. POR FUNCTION

FIGURE 12. TRANSIENT RESPONSE

FN7435.5

August 12, 2005

5

EL7532

Typical Performance Curves (Continued)

JEDEC JESD51-3 LOW EFFECTIVE THERMAL

JEDEC JESD51-7 HIGH EFFECTIVE THERMAL

CONDUCTIVITY TEST BOARD

0.6

1

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

870mW

486mW

0.5

0.4

0.3

0.2

0.1

0

25

50

75 85 100

125

0

25

50

75 85 100

125

AMBIENT TEMPERATURE (°C)

FIGURE 13. PACKAGE POWER DISSIPATION vs AMBIENT

TEMPERATURE

FIGURE 14. PACKAGE POWER DISSIPATION vs AMBIENT

TEMPERATURE

FN7435.5

August 12, 2005

6

EL7532

Where RL is the DC resistance on the inductor and R

the PFET on-resistance, nominal 70mΩ at room temperature

with tempco of 0.2mΩ/°C.

Applications Information

Product Description

DSON1

The EL7532 is a synchronous, integrated FET 2A step-down

regulator which operates from an input of 2.5V to 6V. The

output voltage is user-adjustable with a pair of external

resistors.

As the input voltage drops gradually close or even below the

preset V , the converter gets into 100% duty ratio. At this

O

condition, the upper PFET needs some minimum turn-off

time if it is turned off. This off-time is related to input/output

conditions. This makes the duty ratio appear randomly and

increases the output ripple somewhat until the 100% duty

ratio is reached. A larger output capacitor could reduce the

random-looking ripple. Users need to verify if this condition

has an adverse effect on the overall circuit if close to 100%

duty ratio is expected.

The internally-compensated controller makes it possible to

use only two ceramic capacitors and one inductor to form a

complete, very small footprint 2A DC-DC converter.

Start-Up and Shut-Down

When the EN pin is tied to V , and V reaches

IN

approximately 2.4V, the regulator begins to switch. The

output voltage is gradually increased to ensure proper soft-

start operation.

RSI/POR Function

When powering up, the open-collector Power-On-Reset

output holds low for about 100ms after V reaches the

O

When the EN pin is connected to a logic low, the EL7532 is

in the shut-down mode. All the control circuitry and both

preset voltage. When the active-HI reset signal RSI is

issued, POR goes to low immediately and holds for the

same period of time after RSI comes back to LOW. The

output voltage is unaffected. (Please refer to the timing

diagram). When the function is not used, connect RSI to

MOSFETs are off, and V

falls to zero. In this mode, the

OUT

total input current is less than 1µA.

When the EN reaches logic HI, the regulator repeats the

start-up procedure, including the soft-start function.

ground and leave open the pull-up resister R at POR pin.

4

PWM Operation

The POR output also serves as a 100ms delayed Power

Good signal when the pull-up resister R is installed. The

In the PWM mode, the P channel MOSFET and N channel

MOSFET always operate complementary. When the

PMOSFET is on and the NMOSFET off, the inductor current

increases linearly. The input energy is transferred to the

output and also stored in the inductor. When the P channel

MOSFET is off and the N channel MOSFET on, the inductor

current decreases linearly, and energy is transferred from

the inductor to the output. Hence, the average current

through the inductor is the output current. Since the inductor

and the output capacitor act as a low pass filter, the duty

4

RSI pin needs to be directly (or indirectly through a resister

R ) connected to Ground for this to function properly.

6

V

O

MIN

25ns

RSI

cycle ratio is approximately equal to V divided by V

.

100ms

O

IN

POR

The output LC filter has a second order effect. To maintain

the stability of the converter, the overall controller must be

compensated. This is done with the fixed internally

compensated error amplifier and the PWM compensator.

Because the compensations are fixed, the values of input

and output capacitors are 10µF to 22µF ceramic. The

inductor is nominally 1.8µH, though 1.5µH to 2.2µH can be

used.

FIGURE 15. RSI & POR TIMING DIAGRAM

Output Voltage Selection

Users can set the output voltage of the converter with a

resister divider, which can be chosen based on the following

formula:

100% Duty Ratio Operation

R









2

V

= 0.8 × 1 + ------



EL7532 utilizes CMOS power FET's as the internal

synchronous power switches. The upper switch is a PMOS

and lower switch a NMOS. This not only saves a boot

capacitor, it also allows 100% turn-on of the upper PFET

O



1

Component Selection

Because of the fixed internal compensation, the component

choice is relatively narrow. We recommend 10µF to 22µF

multi-layer ceramic capacitors with X5R or X7R rating for

both the input and output capacitors, and 1.5µH to 2.2µH

inductance for the inductor.

switch, achieving V close to V . The maximum achievable

O

IN

V

is,

O

V

= V – (R + R

) × I

DSON1 O

O

IN

L

FN7435.5

7

August 12, 2005

EL7532

At extreme conditions (V < 3V, I > 0.7A, and junction

Layout Considerations

The layout is very important for the converter to function

properly. The following PC layout guidelines should be

followed:

IN

O

temperature higher than 75°C), input cap C is

1

recommended to be 22µF. Otherwise, if any of the above 3

conditions is not true, C can remain as low as 10µF.

1

The RMS current present at the input capacitor is decided by

the following formula:

• Separate the Power Ground ( ) and Signal Ground ( );

connect them only at one point right at the pins

V

× (V - V

)

• Place the input capacitor as close to V and PGND pins

IN

O

IN

O

-----------------------------------------------

I

=

× I

INRMS

O

V

as possible

IN

• Make the following PC traces as small as possible:

This is about half of the output current I for all the V . This

O

- from L pin to L

X

input capacitor must be able to handle this current.

- from C to PGND

O

The inductor peak-to-peak ripple current is given as:

• If used, connect the trace from the FB pin to R and R as

1

2

close as possible

• Maximize the copper area around the PGND pin

(V - V ) × V

O

IN

O

∆I = --------------------------------------------

IL

L × V × f

IN

S

• Place several via holes under the chip to additional ground

plane to improve heat dissipation

• L is the inductance

• f the switching frequency (nominally 1.5MHz)

S

The demo board is a good example of layout based on this

outline. Please refer to the EL7532 Application Brief.

The inductor must be able to handle I for the RMS load

O

current, and to assure that the inductor is reliable, it must

handle the 3A surge current that can occur during a current

limit condition.

Current Limit and Short-Circuit Protection

The current limit is set at about 3A for the PMOS. When a

short-circuit occurs in the load, the preset current limit

restricts the amount of current available to the output, which

causes the output voltage to drop below the preset voltage.

In the meantime, the excessive current heats up the

regulator until it reaches the thermal shut-down point.

Thermal Shut-Down

Once the junction reaches about 145°C, the regulator shuts

down. Both the P channel and the N channel MOSFETs turn

off. The output voltage will drop to zero. With the output

MOSFETs turned off, the regulator will soon cool down.

Once the junction temperature drops to about 130°C, the

regulator will restart again in the same manner as the EN pin

connects to logic HI.

Thermal Performance

The EL7532 is in a fused-lead MSOP10 package. Compared

to the regular MSOP10 package, the fused-lead package

provides lower thermal resistance. The typical θ of

JA

115°C/W (See Thermal Information section in spec table)

can be improved by maximizing the copper area around the

pins. A θ of 100°C/W can be achieved on a 4-layer board

JA

and 125°C/W on a 2-layer board. Refer to Intersil’s Tech

Brief, TB379, for more information on thermal resistance.

FN7435.5

8

August 12, 2005

EL7532

MSOP Package Outline Drawing

NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at

<http://www.intersil.com/design/packages/index.asp>

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN7435.5

9

August 12, 2005

型号:	EL7532IYZ-T13
Brand Name：	Intersil
生命周期：	Unknown
零件包装代码：	MSOP
包装说明：	TSSOP, TSSOP10,.19,20
针数：	10
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
风险等级：	5.17
模拟集成电路 - 其他类型：	SWITCHING REGULATOR
控制模式：	VOLTAGE-MODE
控制技术：	PULSE WIDTH MODULATION
最大输入电压：	5.5 V
最小输入电压：	2.5 V
标称输入电压：	3.3 V
JESD-30 代码：	S-PDSO-G10
JESD-609代码：	e3
长度：	3 mm
湿度敏感等级：	2
功能数量：	1
端子数量：	10
最高工作温度：	85 °C
最低工作温度：	-40 °C
最大输出电流：	2.4 A
封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP
封装等效代码：	TSSOP10,.19,20
封装形状：	SQUARE
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	260
认证状态：	Not Qualified
座面最大高度：	1.1 mm
子类别：	Switching Regulator or Controllers
表面贴装：	YES
切换器配置：	BUCK
最大切换频率：	1650 kHz
温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn) - annealed
端子形式：	GULL WING
端子节距：	0.5 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	40
宽度：	3 mm
Base Number Matches：	1

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