RM5271™ Microprocessor
with External Cache Interface
Document Rev. 1.3
Date: 02/2000
FEATURES
• Dual Issue superscalar microprocessor
—
200, 250, 266, 300, 350 MHz operating frequencies
—
420 Dhrystone 2.1 MIPS maximum
• High-performance system interface
—
64-bitmultiplexed system address/data bus for optimum
price/performance with up to 125MHz operation frequency
—
High-performance write protocols to maximize uncached
write bandwidth
—
Processor clock multipliers 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9
—
IEEE 1149.1 JTAG boundary scan
• Integrated on-chip caches
—
32KB instruction and 32KB data - 2-way set associative
—
Virtually indexed, physically tagged
—
Write-back and write-through on a per-page basis
—
Pipeline restart on first doubleword for data cache misses
• Integrated secondary cache controller (R5000 compatible)
—
Supports 512K or 2MByte block write-through secondary
• Integrated memory management unit
—
Fully associative joint TLB (shared by I and D translations)
—
48 dual-entries map 96 pages
—
Variable page size (4KB to 16MB in 4x increments)
• High-performance floating point unit - up to 700 MFLOPS
—
Single cycle repeat rate for common single precision opera-
tions and some double precision operations
—
Two cycle repeat rate for double precision multiply and dou-
ble precision combined multiply-add operations
—
Single cycle repeat rate for single precision combined multi-
ply-add operation
• MIPS IV instruction set
—
Floating point multiply-add instruction increases perfor-
mance in signal processing and graphics applications
—
Conditional moves to reduce branch frequency
—
Index address modes (register + register)
• Embedded application enhancements
—
Specialized DSP integer Multiply-Accumulate instructions
and 3-operand multiply instruction
—
Instruction and Data cache locking by set
—
Optional dedicated exception vector for interrupts
• Fully static CMOS design with power down logic
—
Standby reduced power mode with WAIT instruction
—
2.5V core with 3.3V IO’s
• 304-pin SBGA package (31x31mm)
BLOCK DIAGRAM
Extenal Cache Controller
Primary Data Cache
2-way Set Associative
DTag
DTLB
ITag
ITLB
Primary Instruction Cache
2-way Set Associative
A/D Bus
Pad Bus
Store Buffer
Write Buffer
Read Buffer
Pad Buffer
Address Buffer
Instruction Dispatch Unit
FP
Instruction
Register
FP Bus
Integer Bus
Integer
Instruction
Register
D Bus
Floating-Point Control
Floating-Point
Load/Align
Floating-Point
Register File
Packer/Unpacker
Joint TLB
DVA
Load Aligner
Integer Address/Adder
System/Memory
Control
PC Incrementer
FA Bus
IVA
Shifter/Store Aligner
Logic Unit
Floating-Point
MultAdd, Add, Sub,
Cvt, Div, Sqrt
Branch PC Adder
ITLB Virtual
Program Counter
DTLB Virtual
PLL/Clocks
Int Mult, Div, Madd
Quantum Effect Devices
www.qedinc.com
RM5271 Microprocessor, Document Rev. 1.3
Integer Control
Coprocessor 0
Integer Register File
1
ETC [ ETC ]
