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RM5271-300S 参数 Datasheet PDF下载

RM5271-300S图片预览
型号: RM5271-300S
PDF下载: 下载PDF文件 查看货源
内容描述: 64位微处理器\n [64-Bit Microprocessor ]
分类和应用: 微处理器
文件页数/大小: 24 页 / 366 K
品牌: ETC [ ETC ]
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DESCRIPTION  
The QED RM5271 is a highly integrated superscalar micro-  
processor that is ideally suited for high-end embedded con-  
trol applications such as internetworking, high-performance  
image manipulation, high-speed printing, and 3-D visual-  
ization.The RM5271 is also applicable to the low end work-  
station market where its balanced integer and floating-point  
performance and direct support for a large secondary  
cache (up to 2MB) provide outstanding price/performance  
combination with its high-throughput fully pipelined floating-  
point execution unit, the superscalar capability of the  
RM5271 provides unparalleled price/performance in com-  
putationally intensive embedded applications.  
CPU Registers  
The RM5271 CPU contains 32 general purpose registers,  
two special purpose registers for integer multiplication and  
division, a program counter, and no condition code bits.  
Figure 1 shows the user visible state.  
HARDWARE OVERVIEW  
Pipeline  
The RM5271 offers a high-level of integration targeted at  
high-performance embedded applications. The key ele-  
ments of the RM5271 are briefly described below.  
For integer operations, loads, stores, and other non-float-  
ing-point operations, the RM5271 uses a 5-stage pipeline.  
In addition to the 5-stage integer pipeline, the RM5271  
uses an extended 7-stage pipeline for floating-point opera-  
tions.  
Superscalar Dispatch  
The RM5271 has an asymmetric superscalar dispatch unit  
which allows it to issue an integer instruction and a floating-  
point computation instruction simultaneously. With respect  
to superscalar issue, integer instructions include alu,  
branch, load/store, and floating-point load/store, while float-  
ing-point computation instructions include floating-point  
add, subtract, combined multiply-add, converts, etc. In  
Figure 2 shows the RM5271 integer pipeline. Up to five  
integer instructions can be executing simultaneously.  
General Purpose Registers  
63  
0
0
Multiply/Divide Registers  
63  
HI  
0
0
r1  
r2  
63  
LO  
Program Counter  
63  
0
r29  
r30  
r31  
PC  
Figure 1 CPU Registers  
2
RM5271 Microprocessor, Document Rev. 1.3  
Quantum Effect Devices  
www.qedinc.com