NDS9405_NL原理图各脚功能电路原理芯片引脚定义引脚图及功能-中国IC网-芯三七

June 1999

NDS9407

Single P-Channel Enhancement Mode Field Effect Transistor

General Description

Features

These P-Channel enhancement mode power field effect

transistors are produced using Fairchild's proprietary, high cell

density, DMOS technology. This very high density process is

especially tailored to minimize on-state resistance, provide

superior switching performance, and withstand high energy

pulses in the avalanche and commutation modes. These

devices are particularly suited for low voltage applications

such as notebook computer power management and other

battery powered circuits where fast switching, low in-line

power loss, and resistance to transients are needed.

-3.0A, -60V. R_DS(ON)= 0.15W @ V_GS=-10V

R_DS(ON)= 0.24W @ V_GS=-4.5V.

High density cell design for extremely low R_DS(ON)

.

High power and current handling capability in a widely used

surface mount package.

_______________________________________________________________________________________

5

6

7

8

4

3

2

1

Absolute Maximum Ratings

T_A= 25°C unless otherwise noted

Symbol Parameter

NDS9407

Units

Drain-Source Voltage

Gate-Source Voltage

-60

V

V_DSS

V_GSS

I_D

± 20

V

A

± 3.0

± 2.4

± 12

Drain Current - Continuous T_A= 25°C

- Continuous T_A= 70°C

(Note 1a)

-

Pulsed

T_A= 25°C

Maximum Power Dissipation

(Note 1a)

2.5

W

P_D

(Note 1b)

(Note 1c)

1.2

1

Operating and Storage Temperature Range

-55 to 150

°C

T_J,T_STG

THERMAL CHARACTERISTICS

Thermal Resistance, Junction-to-Ambient

Thermal Resistance, Junction-to-Case

(Note 1a)

50

25

°C/W

R

JA

JC

q

(Note 1)

NDS9407.SAM Rev. B

Electrical Characteristics(T_A= 25°C unless otherwise noted)

Symbol Parameter Conditions

OFF CHARACTERISTICS

Drain-Source Breakdown Voltage

Min

Typ

Max

Units

-60

V

BV_DSS

I_DSS

V_GS

V_DS

=

0 V, I_D= -250 µA

-48 V, V_GS0 V

Zero Gate Voltage Drain Current

-1

µA

nA

=

-10

T_A= 55°C

Gate - Body Leakage, Forward

Gate - Body Leakage, Reverse

100

-100

I_GSSF

I_GSSR

V_GS= 20 V, V_DS= 0 V

V_GS= -20 V, V_DS0 V

=

ON CHARACTERISTICS (Note 2)

Gate Threshold Voltage

V_GS(th)

-1

-2.3

-1.8

0.08

0.13

V

V_DS

= V_GS, I_D= -250 µA

-0.8

T_A= 125°C

Static Drain-Source On-Resistance

0.15

0.3

R_DS(ON)

V_GS= -10 V, I_D= -3.0 A

W

0.135

0.2

0.24

0.48

V_GS

=

-4.5 V, I_D

-10 V, V_DS

=

-1.6 A

-5 V

On-State Drain Current

-12

A

S

I_D(on)

g_FS

V_GS

V_DS

=

Forward Transconductance

6.8

-15 V, I_D

= -3.0 A

DYNAMIC CHARACTERISTICS

Input Capacitance

1400

290

80

pF

C_iss

C_oss

C_rss

V_DS

=

-30 V, V_GS= 0 V,

f

= 1.0 MHz

Output Capacitance

Reverse Transfer Capacitance

SWITCHING CHARACTERISTICS (Note 2)

Turn - On Delay Time

Turn - On Rise Time

Turn - Off Delay Time

Turn - Off Fall Time

Total Gate Charge

12

55

22

37

4

30

40

ns

t_D(on)

t_r

t_D(off)

t_f

V_DD= -25 V, I_D= -1 A,

V_GEN-10 V, R_GEN= 6 W

=

100

45

ns

50

nC

Q_g

V_DS= -30 V,

I_D= -3.0 A, V_GS= -10 V

Gate-Source Charge

Gate-Drain Charge

Q_gs

Q_gd

10

NDS9407.SAM Rev. B

Electrical Characteristics(T_A= 25°C unless otherwise noted)

Symbol Parameter Conditions

DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS

Min

Typ

Max

Units

Maximum Continuous Drain-Source Diode Forward Current

Drain-Source Diode Forward Voltage

-2.1

-1.2

A

V

I_S

-0.9

V_SD

Notes:

V_GS= 0 V, I_S= -2.5 A (Note 2)

1. R_qJAis the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R_qJCis

guaranteed by design while R_qCAis determined by the user's board design.

T- T_A

R_qJ(t)

A

T- T_A

R_qJ+_CR_qCA(t)

2

J

P (t) =

D

=

= I (t) ´

D

R

DS(ON)@T_J

Typical R_qJAusing the board layouts shown below on 4.5"x5" FR-4 PCB in astill air environment:

a. 50^oC/W when mounted on a 1 in²pad of 2oz cpper.

b. 105^oC/W when mounted on a 0.04 in²pad of 2oz cpper.

c. 125^oC/W when mounted on a 0.006 in²pad of 2oz cpper.

1a

1b

1c

Scale 1 : 1 on letter size paper

2. Pulse Test: Pulse Width < 300µs, Duty Cycle< 2.0%.

NDS9407.SAM Rev. B

Typical Electrical Characteristics

-20

3

2.5

2

V

= -10V

-7.0

-6.0

V

= -4.0V

GS

-5.5

-4.5

-15

-10

-5

-5.0

-5.5

-4.5

-6.0

1.5

1

-8.0

-10

-4.0

-3.5

0

0.5

0

-1

-2

-3

-4

-5

0

-4

-8

-12

-16

-20

V

, DRAIN-SOURCE VOLTAGE (V)

I

, DRAIN CURRENT (A)

DS

D

Figure 1. On-Region Characteristics.

Figure 2. On-Resistance Variation with Gate Voltage

and Drain Current.

1.8

1.6

1.4

1.2

1

2.5

2

V

= -10V

GS

I

= -3A

D

V

= -10V

GS

T

= 125°C

J

1.5

1

25°C

0.8

-55°C

0.6

0.5

-50

-25

0

25

50

75

100

125

150

0

-5

-10

, DRAIN CURRENT (A)

-15

-20

T

, JUNCTION TEMPERATURE (°C)

J

I

D

Figure 3. On-Resistance Variation

with Temperature.

Figure 4. On-Resistance Variation with Drain Current

and Temperature.

-10

1.2

1.1

1

V

= V

T

J

= -55°C

GS

= -250µA

DS

V

=

-10V

125°C

DS

I

D

-8

-6

-4

-2

0

25°C

0.9

0.8

0.7

-1

-2

-3

-4

-5

-6

-50

-25

0

25

50

75

100

125

150

V

, GATE TO SOURCE VOLTAGE (V)

T , JUNCTION TEMPERATURE (°C)

GS

J

Figure 6. Gate Threshold Variation with

Temperature.

Figure 5. Transfer Characteristics.

NDS9407.SAM Rev. B

Typical Electrical Characteristics(continued)

1.125

10

V

= 0V

5

I

= -250µA

1.1

1.075

1.05

GS

D

1

T

J

= 125°C

0.5

25°C

1.025

1

-55°C

0.1

0.01

0.975

0.95

0.925

0.9

0.001

-50

-25

0

25

50

75

100

125

150

0.2

0.4

0.6

0.8

1

1.2

1.4

T

, JUNCTION TEMPERATURE (°C)

J

-V

, BODY DIODE FORWARD VOLTAGE (V)

SD

Figure 7. Breakdown Voltage Variation with

Temperature.

Figure 8. Body Diode Forward Voltage Variation

with Current and Temperature

2500

10

8

C

V

= -10V

iss

I

= -3A

DS

1500

1000

DS

-40V

-20V

6

500

C

oss

4

200

100

50

f

= 1 MHz

2

C

rss

V

=

0V

GS

0

0.1

0.2

0.5

DS

1

2

5

10

20

50

0

10

20

, GATE CHARGE (nC)

30

40

-V

, DRAIN TO SOURCE VOLTAGE (V)

Q

g

Figure 9. Capacitance Characteristics.

Figure 10. Gate Charge Characteristics.

-V_DD

t _{o n}

t _off

t _d(off)

t _{d ( o n )}

t_r

t _f

R _L

9 0 %

V _IN

9 0 %

D

V _{O U T}

V

O U T

V_{G S}

1 0 %

9 0 %

R _GEN

D U T

G

V

5 0 %

IN

S

1 0 %

INVERTED

P U L S E W I D T H

Figure 11. Switching Test Circuit

Figure 12. Switching Waveforms

NDS9407.SAM Rev. B

Typical Electrical and Thermal Characteristics(continued)

2.5

14

V

= -10V

DS

1a

T

= -55°C

J

12

10

8

2

1.5

1

25°C

125°C

1b

1c

6

4

4.5"x5" FR-4 Board

o

T

= 25 C

2

A

Still Air

0.5

0

0.2

0.4

0.6

0.8

1

0

-4

-8

-12

-16

-20

2

2oz COPPER MOUNTING PAD AREA (in

)

I

, DRAIN CURRENT (A)

D

Figure 14. SO-8 Maximum Steady-State Power

Dissipation versus Copper Mounting Pad

Area.

Figure 13. Transconductance Variation with Drain

Current and Temperature

4

20

10

1a

3

2

1

0

3

1

1b

1c

0.3

V

=

-10V

SINGLE PULSE

See Note 1c

25°C

GS

0.1

4.5"x5" FR-4 Board

o

R

=

JA

q

T

= 25 C

A

0.03

0.01

T

=

Still Air

A

V

=

- 1 0 V

GS

0

0.2

0.4

0.6

0.8

1

0.1

0.2

0.5

- V

1

5

10

20

60 100

2

2oz COPPER MOUNTING PAD AREA (in

)

, DRAIN-SOURCE VOLTAGE (V)

DS

Figure 16. Maximum Safe Operating Area

Figure 15. Maximum Steady- State Drain Current

versus Copper Mounting Pad Area.

1

0.5

D = 0.5

0.2

0.1

R

(t) = r(t) * R

JA

q

JA

q

R

0.1

0.05

= See Note 1c

q

0.05

P(pk)

0.02

0.01

Single Pulse

0.02

0.01

t₁

t₂

0.005

T

- T = P * R

(t)

J

A

qJA

Duty Cycle, D = t ₁/ t

2

0.002

0.001

0.0001

0.001

0.01

0.1

1

10

100

300

1

t , TIME (sec)

Figure 17. Transient Thermal Response Curve.

Note: Thermal characterization performed using the conditions described in note 1c. Transient thermal response will

change depending on the circuit board design.

NDS9407.SAM Rev. B

SO-8 Tape and Reel Data and Package Dimensions

SOIC(8lds) Packaging

Configuration: Figure 1.0

Packaging Description:

SOIC-8 parts are shipped in tape. The carrier tape is

ELECTROSTATIC

SENSITIVE DEVICES

DO NO

T

S

M

HI

P

OR

S

TO

RE

N

E

AR

S

T

RO NG

E

L

E

CTROS

T

ATIC

made from dissipative (carbon filled) polycarbonate

a

E

L

E

CTRO

AGN

E

TI

C,

M

AG NE

T

IC

O

R R ADIO ACTIVE FI ELD S

TNR DATE

PT NUMB E

resin. The cover tape is a multilayer film (Heat Activated

Adhesive in nature) primarily composed of polyester film,

adhesive layer, sealant, and anti-static sprayed agent.

These reeled parts in standard option are shipped with

2,500 units per 13" or 330cm diameter reel. The reels are

dark blue in color and is made of polystyrene plastic (anti-

static coated). Other option comes in 500 units per 7" or

177cm diameter reel. This and some other options are

further described in the Packaging Information table.

R

PEEL STRENGTH MIN ______________gms

MAX _____________gms

Antistatic Cover Tape

ESD Label

These full reels are individually barcode labeled and

placed inside

a standard intermediate box (illustrated in

figure 1.0) made of recyclable corrugated brown paper.

One box contains two reels maximum. And these boxes

are placed inside

comes in different sizes depending on the number of parts

shipped.

a barcode labeled shipping box which

Static Dissipative

Embossed Carrier Tape

F63TNR

Label

F

NDS

9959

852

Customized

Label

F

Pin 1

SOIC (8lds) Packaging Information

Standard

L86Z

F011

D84Z

Packaging Option

(no flow code)

SOIC-8 Unit Orientation

Packaging type

TNR

2,500

Rail/Tube

TNR

4,000

TNR

500

Qty per Reel/Tube/Bag

Reel Size

95

-

13" Dia

7" Dia

Box Dimension (mm)

Max qty per Box

343x64x343 530x130x83 343x64x343 184x187x47

5,000

0.0774

0.6060

30,000

0.0774

-

8,000

0.0774

0.9696

1,000

0.0774

0.1182

Weight per unit (gm)

Weight per Reel (kg)

Note/Comments

343mm x 342mm x 64mm

Standard Intermediate box

ESD Label

F63TNR Label sample

F63TNLabel

ESD Label

F63TN Label

LOT: CBVK741B019

FSID: FDS9953A

QTY: 2500

SPEC:

D/C1: D9842

D/C2:

QTY1:

QTY2:

SPEC REV:

CPN:

N/F: F

(F63TNR)3

SOIC(8lds) Tape Leader and Trailer

Configuration: Figure 2.0

Carrier Tape

Cover Tape

Components

Trailer Tape

Leader Tape

640mm minimum or

80 empty pockets

1680mm minimum or

210 empty pockets

July 1999, Rev. B

SO-8 Tape and Reel Data and Package Dimensions, continued

SOIC(8lds) Embossed Carrier Tape

Configuration: Figure 3.0

P0

D0

T

E1

E2

F

W

K0

Wc

B0

Tc

A0

D1

P1

User Direction of Feed

Dimensions are in millimeter

A0

B0

W

D0

D1

E1

E2

F

P1

P0

K0

T

Wc

Tc

Pkg type

0.450

+/-

0.150

(8lds)

SOIC

(12mm)

6.50

+/-0.10

5.30

+/-0.10

12.0

+/-0.3

1.55

+/-0.05

1.60

+/-0.10

1.75

+/-0.10

10.25

min

5.50

+/-0.05

8.0

+/-0.1

4.0

+/-0.1

2.1

+/-0.10

9.2

+/-0.3

0.06

+/-0.02

Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481

rotational and lateral movement requirements (see sketches A, B, and C).

0.5mm

maximum

20 deg maximum

Typical

component

cavity

center line

0.5mm

maximum

B0

20 deg maximum component rotation

Typical

component

center line

Sketch A (Side or Front Sectional View)

Component Rotation

Sketch C (Top View)

Component lateral movement

A0

Sketch B (Top View)

Component Rotation

SOIC(8lds) Reel Configuration: Figure 4.0

W1 Measured at Hub

Dim A

Max

Dim A

max

See detail AA

Dim N

7"Diameter Option

B Min

Dim C

See detail AA

Dim D

min

W3

13" Diameter Option

W2 max Measured at Hub

DETAIL AA

Dim W2

Dimensions are in inches and millimeters

Reel

Option

Tape Size

12mm

Dim A

Dim B

Dim C

Dim D

Dim N

Dim W1

Dim W3 (LSL-USL)

7.00

177.8

0.059

1.5

512 +0.020/-0.008

13 +0.5/-0.2

0.795

20.2

2.165

55

0.488 +0.078/-0.000

12.4 +2/0

0.724

18.4

0.469 – 0.606

11.9 – 15.4

7" Dia

13.00

330

0.059

1.5

512 +0.020/-0.008

13 +0.5/-0.2

0.795

20.2

7.00

178

0.488 +0.078/-0.000

12.4 +2/0

0.724

18.4

0.469 – 0.606

11.9 – 15.4

12mm

13" Dia

1998 Fairchild Semiconductor Corporation

July 1999, Rev. B

SO-8 Tape and Reel Data and Package Dimensions, continued

SOIC-8 (FS PKG Code S1)

1 : 1

Scale 1:1 on letter size paper

Dimensions shown below are in:

inches [millimeters]

Part Weight per unit (gram): 0.0774

9

September 1998, Rev. A

TRADEMARKS

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is

not intended to be an exhaustive list of all such trademarks.

ACEx™

CoolFET™

ISOPLANAR™

MICROWIRE™

POP™

PowerTrench

QFET™

SyncFET™

TinyLogic™

UHC™

CROSSVOLT™

E²CMOS^TM

VCX™

FACT™

FACT Quiet Series™

QS™

FAST^®

Quiet Series™

SuperSOT™-3

SuperSOT™-6

SuperSOT™-8

FASTr™

GTO™

HiSeC™

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER

NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD

DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT

OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT

RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.

As used herein:

1. Life support devices or systems are devices or

systems which, (a) are intended for surgical implant into

the body, or (b) support or sustain life, or (c) whose

failure to perform when properly used in accordance

with instructions for use provided in the labeling, can be

reasonably expected to result in significant injury to the

user.

2. A critical component is any component of a life

support device or system whose failure to perform can

be reasonably expected to cause the failure of the life

support device or system, or to affect its safety or

effectiveness.

PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification

Product Status

Definition

Advance Information

Formative or

In Design

This datasheet contains the design specifications for

product development. Specifications may change in

any manner without notice.

Preliminary

First Production

This datasheet contains preliminary data, and

supplementary data will be published at a later date.

Fairchild Semiconductor reserves the right to make

changes at any time without notice in order to improve

design.

No Identification Needed

Obsolete

Full Production

This datasheet contains final specifications. Fairchild

Semiconductor reserves the right to make changes at

any time without notice in order to improve design.

Not In Production

This datasheet contains specifications on a product

that has been discontinued by Fairchild semiconductor.

The datasheet is printed for reference information only.

Rev. D

型号:	NDS9407
是否Rohs认证：	不符合
生命周期：	Transferred
包装说明：	SMALL OUTLINE, R-PDSO-G8
Reach Compliance Code：	unknown
ECCN代码：	EAR99
风险等级：	5.8
Is Samacsys：	N
配置：	SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压：	60 V
最大漏极电流 (Abs) (ID)：	3 A
最大漏极电流 (ID)：	3 A
最大漏源导通电阻：	0.15 Ω
FET 技术：	METAL-OXIDE SEMICONDUCTOR
JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e0
元件数量：	1
端子数量：	8
工作模式：	ENHANCEMENT MODE
最高工作温度：	150 °C
封装主体材料：	PLASTIC/EPOXY
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
极性/信道类型：	P-CHANNEL
功耗环境最大值：	1 W
最大功率耗散 (Abs)：	2.5 W
认证状态：	Not Qualified
子类别：	Other Transistors
表面贴装：	YES
端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING
端子位置：	DUAL
晶体管应用：	SWITCHING
晶体管元件材料：	SILICON
Base Number Matches：	1

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