V
DD1
A0
A1
A2
A3
A4
A5
E2
V
SS
E3
W0
A6
A7
A8
A9
A10
V
DD2
DEVICE OPERATION
DQ0(2)
DQ1(2)
DQ2(2)
DQ3(2)
DQ4(2)
DQ5(2)
DQ6(2)
DQ7(2)
V
SS
DQ0(3)
DQ1(3)
DQ2(3)
DQ3(3)
DQ4(3)
DQ5(3)
DQ6(3)
DQ7(3)
DQ0(0)
DQ1(0)
DQ2(0)
DQ3(0)
DQ4(0)
DQ5(0)
DQ6(0)
DQ7(0)
V
SS
DQ0(1)
DQ1(1)
DQ2(1)
DQ3(1)
DQ4(1)
DQ5(1)
DQ6(1)
DQ7(1)
68 67 66 65 64 63 62 61 60 59 58 57 56 555453 52
1
51
2
50
3
49
4
48
5
47
Top View
6
46
7
45
8
44
9
43
10
42
11
41
12
40
13
39
14
38
15
37
16
36
17
35
1819 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
V
DD2
A11
A12
A13
A14
A15
A16
E0
G
E1
A17
W1
W2
W3
A18
V
DD1
V
SS
Each die in the UT8CR512K32 has three control inputs called
Enable (En), Write Enable (Wn), and Output Enable (G); 19
address inputs, A(18:0); and eight bidirectional data lines,
DQ(7:0). The device enable (En) controls device selection,
active, and standby modes. Asserting En enables the device,
causes I
DD
to rise to its active value, and decodes the 19 address
inputs to each memory die by selecting the 2,048,000 byte of
memory. Wn controls read and write operations. During a read
cycle, G must be asserted to enable the outputs.
Table 1. Device Operation Truth Table
G
X
X
1
0
WN
X
0
1
1
EN
1
0
0
0
I/O Mode
3-state
Data in
3-state
Data out
Mode
Standby
Write
Read
2
Read
Figure 2. 17ns SRAM Pinout 68)
PIN NAMES
A(18:0)
DQ(7:0)
EN
W
G
V
DD1
V
DD2
V
SS
Address
Data Input/Output
Enable
Write Enable
Output Enable
Power (1.8V)
Power (3.3V)
Ground
Notes:
1. “X” is defined as a “don’t care” condition.
2. Device active; outputs disabled.
READ CYCLE
A combination of Wn greater than V
IH
(min) with En and G less
than V
IL
(max) defines a read cycle. Read access time is
measured from the latter of device enable, output enable, or valid
address to valid data output.
SRAM read Cycle 1, the Address Access is initiated by a change
in address inputs while the chip is enabled with G asserted and
Wn deasserted. Valid data appears on data outputs DQn(7:0)
after the specified t
AVQV
is satisfied. Outputs remain active
throughout the entire cycle. As long as device enable and output
enable are active, the address inputs may change at a rate equal
to the minimum read cycle time (t
AVAV
).
SRAM read Cycle 2, the Chip Enable-controlled Access is
initiated by En going active while G remains asserted, Wn
remains deasserted, and the addresses remain stable for the
entire cycle. After the specified t
ETQV
is satisfied, the eight-bit
word addressed by A(18:0) is accessed and appears at the data
outputs DQn(7:0).
SRAM read Cycle 3, the Output Enable-controlled Access is
initiated by G going active while En is asserted, Wn is
deasserted, and the addresses are stable. Read access time is
t
GLQV
unless t
AVQV
or t
ETQV
have not been satisfied.
2
AEROFLEX [ AEROFLEX CIRCUIT TECHNOLOGY ]
