WRITE CYCLE
A combination of Wn less than V
IL
(max) and En less than
V
IL
(max) defines a write cycle. The state of G is a “don’t care”
for a write cycle. The outputs are placed in the high-impedance
state when either G is greater than V
IH
(min), or when Wn is less
than V
IL
(max).
Write Cycle 1, the Write Enable-controlled Access is defined
by a write terminated by Wn going high, with En still active.
The write pulse width is defined by t
WLWH
when the write is
initiated by Wn, and by t
ETWH
when the write is initiated by En.
Unless the outputs have been previously placed in the high-
impedance state by G, the user must wait t
WLQZ
before applying
data to the eight bidirectional pins DQn(7:0) to avoid bus
contention.
Write Cycle 2, the Chip Enable-controlled Access is defined by
a write terminated by the former of En or Wn going inactive.
The write pulse width is defined by t
WLEF
when the write is
initiated by Wn, and by t
ETEF
when the write is initiated by the
En going active. For the Wn initiated write, unless the outputs
have been previously placed in the high-impedance state by G,
the user must wait t
WLQZ
before applying data to the eight
bidirectional pins DQn (7:0) to avoid bus contention.
RADIATION HARDNESS
The UT8CR512K32 SRAM incorporates special design and
layout features which allows operation in a limited radiation
environment.
Table 2. Radiation Hardness
Design Specifications
1
Total Dose
Heavy Ion
Error Rate
2
300K
8.9x10
-10
rad(Si)
Errors/Bit-Day
Notes:
1. The SRAM is immune to latchup to particles >100MeV-cm
2
/mg.
2. 10% worst case particle environment, Geosynchronous orbit, 100 mils of
Aluminum.
Supply Sequencing
No supply voltage sequencing is required between V
DD1
and
V
DD2
.
3
AEROFLEX [ AEROFLEX CIRCUIT TECHNOLOGY ]
