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    PIC18F8490-I/PT 参数 Datasheet PDF下载

    PIC18F8490-I/PT图片预览
    型号： PIC18F8490-I/PT
    PDF下载： 下载PDF文件 查看货源
    内容描述： 八十〇分之六十四引脚闪存微控制器与LCD驱动器和纳瓦技术 [64/80-Pin Flash Microcontrollers with LCD Driver and nanoWatt Technology]
    分类和应用： 驱动器闪存微控制器
    文件页数/大小： 414 页 / 6891 K
    品牌： MICROCHIP [ MICROCHIP TECHNOLOGY ]
     浏览型号PIC18F8490-I/PT的Datasheet PDF文件第397页浏览型号PIC18F8490-I/PT的Datasheet PDF文件第398页浏览型号PIC18F8490-I/PT的Datasheet PDF文件第399页浏览型号PIC18F8490-I/PT的Datasheet PDF文件第400页浏览型号PIC18F8490-I/PT的Datasheet PDF文件第402页浏览型号PIC18F8490-I/PT的Datasheet PDF文件第403页浏览型号PIC18F8490-I/PT的Datasheet PDF文件第404页浏览型号PIC18F8490-I/PT的Datasheet PDF文件第405页  
    PIC18F6390/6490/8390/8490
    INDEX
    A
    A/D ................................................................................... 231
    A/D Converter Interrupt, Configuring ....................... 235
    Acquisition Requirements ........................................ 236
    ADCON0 Register .................................................... 231
    ADCON1 Register .................................................... 231
    ADCON2 Register .................................................... 231
    ADRESH Register ............................................ 231, 234
    ADRESL Register .................................................... 231
    Analog Port Pins, Configuring .................................. 238
    Associated Registers ............................................... 240
    Automatic Acquisition Time ...................................... 237
    Configuring the Module ............................................ 235
    Conversion Clock (T
    AD
    ) ........................................... 237
    Conversion Status (GO/DONE Bit) .......................... 234
    Conversions ............................................................. 239
    Converter Characteristics ........................................ 384
    Discharge ................................................................. 239
    Operation in Power-Managed Modes ...................... 238
    Special Event Trigger (CCP) .................................... 240
    Use of the CCP2 Trigger .......................................... 240
    Absolute Maximum Ratings ............................................. 349
    AC (Timing) Characteristics ............................................. 367
    Load Conditions for Device Timing
    Specifications ................................................... 368
    Parameter Symbology ............................................. 367
    Temperature and Voltage Specifications ................. 368
    Timing Conditions .................................................... 368
    Access Bank ...................................................................... 73
    Mapping with Indexed Literal Offset Mode ................. 86
    ACKSTAT ........................................................................ 187
    ACKSTAT Status Flag ..................................................... 187
    ADCON0 Register ............................................................ 231
    GO/DONE Bit ........................................................... 234
    ADCON1 Register ............................................................ 231
    ADCON2 Register ............................................................ 231
    ADDFSR .......................................................................... 338
    ADDLW ............................................................................ 301
    Addressable Universal Synchronous Asynchronous
    Receiver Transmitter (AUSART).
    See
    AUSART.
    ADDULNK ........................................................................ 338
    ADDWF ............................................................................ 301
    ADDWFC ......................................................................... 302
    ADRESH Register ............................................................ 231
    ADRESL Register .................................................... 231, 234
    Analog-to-Digital Converter.
    See
    A/D.
    ANDLW ............................................................................ 302
    ANDWF ............................................................................ 303
    Assembler
    MPASM Assembler .................................................. 346
    AUSART
    Asynchronous Mode ................................................ 222
    Associated Registers, Receive ........................ 225
    Associated Registers, Transmit ....................... 223
    Receiver ........................................................... 224
    Setting up 9-Bit Mode with
    Address Detect ........................................ 224
    Transmitter ....................................................... 222
    Baud Rate Generator (BRG) ................................... 220
    Associated Registers ....................................... 220
    Baud Rate Error, Calculating ........................... 220
    Baud Rates, Asynchronous Modes ................. 221
    High Baud Rate Select (BRGH Bit) ................. 220
    Operation in Power-Managed Modes .............. 220
    Sampling ......................................................... 220
    Synchronous Master Mode ...................................... 226
    Associated Registers, Receive ........................ 228
    Associated Registers, Transmit ....................... 227
    Reception ........................................................ 228
    Transmission ................................................... 226
    Synchronous Slave Mode ........................................ 229
    Associated Registers, Receive ........................ 230
    Associated Registers, Transmit ....................... 229
    Reception ........................................................ 230
    Transmission ................................................... 229
    Auto-Wake-up on Sync Break Character ......................... 210
    B
    Bank Select Register (BSR) .............................................. 71
    Baud Rate Generator ...................................................... 183
    BC .................................................................................... 303
    BCF ................................................................................. 304
    BF .................................................................................... 187
    BF Status Flag ................................................................. 187
    Block Diagrams
    A/D ........................................................................... 234
    Analog Input Model .................................................. 235
    AUSART Receive .................................................... 224
    AUSART Transmit ................................................... 222
    Baud Rate Generator .............................................. 183
    Capture Mode Operation ......................................... 150
    Comparator Analog Input Model .............................. 245
    Comparator I/O Operating Modes ........................... 242
    Comparator Output .................................................. 244
    Comparator Voltage Reference ............................... 248
    Compare Mode Operation ....................................... 151
    Device Clock .............................................................. 36
    EUSART Receive .................................................... 208
    EUSART Transmit ................................................... 206
    External Power-on Reset Circuit
    (Slow V
    DD
    Power-up) ........................................ 53
    Fail-Safe Clock Monitor ........................................... 290
    Generic I/O Port Operation ...................................... 109
    HLVD Module (with External Input) ......................... 252
    Interrupt Logic ............................................................ 94
    LCD Clock Generation ............................................. 262
    LCD Driver Module .................................................. 257
    LCD Resistor Ladder Connection ............................ 263
    MSSP (I
    2
    C Master Mode) ........................................ 181
    MSSP (I
    2
    C Mode) .................................................... 166
    MSSP (SPI Mode) ................................................... 157
    On-Chip Reset Circuit ................................................ 51
    PLL (HS Mode) .......................................................... 33
    PWM Operation (Simplified) .................................... 153
    Reads from Flash Program Memory ......................... 88
    Single Comparator ................................................... 243
    Table Read Operation ............................................... 87
    Timer0 in 16-Bit Mode ............................................. 132
    ©
    2007 Microchip Technology Inc.
    DS39629C-page 399

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