64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Timing Diagrams
Figure 46:
A[21:0]
V
IH
V
IL
V
IH
VALID ADDRESS
VALID ADDRESS
tAW
tWR
tAA
Asynchronous WRITE Followed by Asynchronous READ – ADV# LOW
VALID ADDRESS
ADV#
LB#/UB#
V
IL
V
IH
V
IL
tCW
tCPH
1
tCO
tHZ
tBW
tBLZ
tBHZ
CE#
V
IH
V
IL
tLZ
tOHZ
tOE
tWC
tWPH
OE#
V
IH
V
IL
tWP
WE#
V
IH
V
IL
V
OH
V
OL
tWHZ
High-Z
tOLZ
tHZ
tHZ
WAIT
DQ[15:0]
V
IH
IN/OUT
V
IL
DATA
tDH
DATA
tDW
High-Z
V
OH
V
OL
VALID
OUTPUT
DON’T CARE
UNDEFINED
Notes: 1. When configured for synchronous mode (BCR[15] = 0), CE# must remain HIGH for at least
5ns (
t
CPH) to schedule the appropriate internal refresh operation. Otherwise,
t
CPH is only
required after CE#-controlled WRITEs.
Table 43:
WRITE Timing Parameters – ADV# LOW
-70x
-856
Min
85
85
5
85
0
23
Max
Units
ns
ns
ns
ns
ns
ns
Symbol
t
HZ
t
WC
t
WHZ
t
-70x
Min
70
8
46
10
0
55
10
0
Max
8
85
-856
Min
Max
8
8
Units
ns
ns
ns
ns
ns
ns
Symbol
t
AW
t
BW
t
CPH
t
Min
70
70
5
70
0
23
Max
CW
WP
t
DH
t
DW
t
WPH
t
WR
Table 44:
READ Timing Parameters – ADV# LOW
-70x
-856
Min
Max
85
8
10
70
8
85
8
Units
ns
ns
ns
�½σ
ns
Symbol
t
LZ
t
t
-70x
Min
10
20
8
8
Max
-856
Min
10
20
8
5
Max
Units
ns
ns
ns
ns
Symbol
t
AA
t
Min
Max
70
8
BHZ
t
BLZ
t
CO
t
HZ
10
OE
OHZ
t
OLZ
5
PDF: 09005aef80be1fbd/Source: 09005aef80be2036
Burst CellularRAM_2.fm - Rev. G 10/05 EN
57
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
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