64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Timing Diagrams
Figure 43:
CLK
A[21:0]
ADV#
LB#/UB#
CE#
OE#
WE#
WAIT
Asynchronous WRITE Followed By Burst READ – ADV# LOW
V
IH
V
IL
tWC
tWC
VALID ADDRESS
tWR
tAW
tCKA
tSP
tCLK
tHD
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
IH
VALID ADDRESS
VALID
ADDRESS
tSP
tHD
tBW
tSP tHD
tCW
tCBPH
2
tCSP
tABA
tOHZ
tWC
tWPH
tWP
tSP tHD
tCEW
tBOE
tKOH
High-Z
tWHZ
High-Z
DATA
tDH
DQ[15:0]
IN/OUT
V
IL
DATA
tDW
V
OH
V
OL
tACLK
High-Z
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
DON’T CARE
UNDEFINED
Notes: 1. Non-default BCR settings for asynchronous WRITE followed by burst READ—ADV# LOW:
Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2. When configured for synchronous mode (BCR[15] = 0), a refresh opportunity must be pro-
vided every
t
CEM. A refresh opportunity is satisfied by either of the following two condi-
tions: a) clocked CE# HIGH, or b) CE# HIGH for greater than 15ns. Note that CellularRAM
Working Group 1.0 specification requires CE# to be clocked HIGH to terminate the burst.
3. Clock rates below 50 MHz (
t
CLK > 20ns) are allowed as long as
t
CSP specifications are met.
Table 37:
Asynchronous WRITE Timing Parameters – ADV# LOW
-70x
-856
Min
85
85
85
85
0
23
Max
Units
ns
ns
ns
ns
ns
ns
Symbol
t
-70x
Min
70
8
46
10
0
55
10
0
Max
-856
Min
85
8
Max
Units
ns
ns
ns
ns
ns
Symbol
t
Min
70
70
70
70
0
23
Max
AW
t
BW
t
CKA
t
CW
t
DH
t
DW
WC
t
WHZ
t
WP
t
WPH
t
WR
Table 38:
Burst READ Timing Parameters
-708
-706/-856
Min
Max
56
11
20
5
1
15
7.5
20
Units
ns
ns
ns
ns
ns
ns
Symbol
t
CSP
t
-708
Min
4.5
2
2
3
Max
20
-706/-856
Min
5
2
2
3
Max
20
Units
ns
ns
ns
ns
ns
Symbol
t
ABA
t
Min
Max
46.5
9
20
ACLK
5
1
12.5
HD
t
BOE
t
CBPH
t
CEW
t
CLK
t
KOH
t
OHZ
t
SP
8
8
7.5
20
PDF: 09005aef80be1fbd/Source: 09005aef80be2036
Burst CellularRAM_2.fm - Rev. G 10/05 EN
54
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
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