Core1553BRT-EBR Enhanced Bit Rate 1553 Remote Terminal
General Description
Core1553BRT-EBR provides a complete, dual-redundant 1553 enhanced bit rate (EBR) remote terminal (RT) apart from
the transceivers required to interface to the bus. A typical system implementation using the Core1553BRT-EBR is shown
in
and
ADC
Backend
Interface
BUSAIN
BUSAINENn
BUSAOUTEN
BUSAOUT
RS485
Transceivers
BUSBIN
BUSBINENn
BUSBOUTEN
BUSBOUT
Glue
Logic
Memory
Command
Illegality
Block
Actel FPGA
Figure 1 •
Typical Core1553BRT-EBR System
At a high level, Core1553BRT-EBR simply provides a set of
memory mapped sub-addresses that "receive data
written to" or "transmit data read from." The core can
be configured to directly connect to synchronous or
asynchronous memory devices. Alternately, the core can
directly connect to the backend devices, removing the
need for the memory buffers. If memory is used, the core
Command
Legality
Block
Core1553BRT-EBR
requires 2,048 words of memory, which can be shared
with the local CPU.
The core supports all 1553EBR mode codes and allows
the user to designate as illegal any mode code or any
particular sub-address for both transmit and receive
operations. The command legalization can be done
within the core or in an external command legality block
via the command legalization interface.
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A d v a n c e d v 1 .1
ACTEL [ Actel Corporation ]
