bq3285LF
Block Diagram
X1
X2
Time-
Base
Oscillator
÷8
÷ 64
÷ 64
3
4
16
:
1 MUX
RST
MOT
CS
R/W
AS
AD0–AD7
Control/Status
Registers
32K
Driver
32K
µ
P
Bus
I/F
Clock/Calendar, Alarm
and Control Bytes
Interupt
Generator
INT
DS
EXTRAM
RCL
MUX
User Buffer
(14 Bytes)
Storage Registers
(114 Bytes)
Storage Registers
(126 Bytes)
Control/Calendar
Update
CS
VCC
BC
Power-
Fail
Control
VOUT
Write
Protect
Index Registers
(2 Bytes)
BD3285ID.eps
Pin Descriptions
MOT
Bus type select input
MOT selects bus timing for either Motorola
or Intel architecture. This pin should be
tied to V
CC
for Motorola timing or to V
SS
for
Intel timing (see Table 1). The setting
should not be changed during system opera-
tion. MOT is internally pulled low by a 30K
Ω
resistor.
AD
0
–AD
7
Multiplexed address/data
input/output
The bq3285LF bus cycle consists of two
phas es : t he add re s s phas e and the
data-transfer phase. The address phase
precedes the data-transfer phase. During
the address phase, an address placed on
AD
0
–AD
7
is latched into the bq3285LF on
the falling edge of the AS signal. During
the data-transfer phase of the bus cycle, the
AD0–AD
7
pins serve as a bidirectional data
bus.
Table 1. Bus Setup
AS
Bus
Type
Motorola
Intel
MOT
DS
R/W
AS
Level Equivalent Equivalent Equivalent
V
CC
V
SS
DS, E, or
Φ2
RD,
MEMR, or
I/OR
R/W
AS
Address strobe input
AS serves to demultiplex the address/data
bus. The falling edge of AS latches the ad-
dress on AD
0
–AD
7
. This demultiplexing pro-
cess is independent of the CS signal. For
DIP and SOIC packages with MOT = V
SS
,
the AS input is provided a signal similar to
ALE in an Intel-based system.
WR,
MEMW, or ALE
I/OW
2
TI [ TEXAS INSTRUMENTS ]
