64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Timing Diagrams
Figure 30:
Single-Access Burst READ Operation
t
CLK
t
KP
t
KP
t
KHKL
V
IH
CLK
V
IL
V
IH
V
IL
V
IH
t
SP
t
HD
A[21:0]
VALID
ADDRESS
t
SP
t
HD
ADV#
V
IL
t
CEM
t
HD
t
HZ
t
CSP
t
ABA
CE#
V
IH
V
IL
t
BOE
t
OHZ
V
IH
OE#
V
IL
t
SP
t
HD
t
OLZ
WE#
V
IH
V
IL
t
SP
t
HD
V
IH
LB#/UB#
V
IL
V
OH
t
CEW
t
KHTL
WAIT
V
OL
V
OH
V
OL
High-Z
t
ACLK
t
KOH
High-Z
DQ[15:0]
High-Z
VALID
OUTPUT
READ Burst Identified
(WE# = HIGH)
DON’T CARE
UNDEFINED
Notes: 1. Non-default BCR settings for single-access burst READ operation: Latency code two (three
clocks); WAIT active LOW; WAIT asserted during delay.
2. Clock rates below 50 MHz (
t
CLK > 20ns) are allowed as long as
t
CSP specifications are met.
Table 22:
Burst READ Timing Parameters – Single Access
-708
-706/-856
Min
Max
56
11
20
8
7.5
20
20
Units
ns
ns
ns
µs
ns
ns
ns
ns
Symbol
t
HZ
t
KHKL
t
KHTL
t
t
-708
Min
Max
8
1.8
9
2
4
8
5
3
-706/-856
Min
Max
8
2.0
11
2
5
8
5
3
Units
ns
ns
ns
ns
ns
ns
ns
ns
Symbol
t
ABA
t
ACLK
t
BOE
t
Min
Max
46.5
9
20
8
7.5
20
20
CEM
t
CEW
t
CLK
t
CSP
t
HD
1
12.5
4.5
2
1
15
5
2
KOH
KP
t
OHZ
t
OLZ
t
SP
PDF: 09005aef80be1fbd/Source: 09005aef80be2036
Burst CellularRAM_2.fm - Rev. G 10/05 EN
41
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
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