64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Timing Diagrams
Figure 34:
Continuous Burst READ Showing an Output Delay with BCR[8] = 0 for End-of-Row
Condition
V
IH
V
IL
tCLK
CLK
A[21:0]
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
tKHTL
tKHTL
NOTE 3
V
OH
V
OL
V
OH
V
OL
NOTE 4
ADV#
LB#/UB#
CE#
OE#
WE#
WAIT
DQ[15:0]
VALID
OUTPUT
VALID
OUTPUT
tACLK
VALID
OUTPUT
VALID
OUTPUT
tKOH
DON’T CARE
Notes: 1. Non-default BCR settings for continuous burst READ, showing an output delay, with
BCR[8] = 0 for end-of-row condition: Latency code two (three clocks); WAIT active LOW;
WAIT asserted during delay.
2. Clock rates below 50 MHz (
t
CLK > 20ns) are allowed as long as
t
CSP specifications are met.
3. WAIT will be asserted a maximum of (2 x LC) cycles (BCR[8] = 0; WAIT asserted during
delay). LC = Latency Code (BCR[13:11]).
4. CE# must not remain LOW longer than
t
CEM.
Table 26:
Burst READ Timing Parameters – BCR[8] = 0
-708
-706/-856
Min
15
Max
11
20
Units
ns
ns
Symbol
t
t
-708
Min
2
Max
9
-706/-856
Min
2
Max
11
Units
ns
ns
Symbol
t
Min
12.5
Max
9
20
ACLK
t
CLK
KHTL
KOH
PDF: 09005aef80be1fbd/Source: 09005aef80be2036
Burst CellularRAM_2.fm - Rev. G 10/05 EN
45
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©2003 Micron Technology, Inc. All rights reserved.
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