64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Timing Diagrams
Figure 39:
Burst WRITE Operation
tCLK
tKP
tKP
tKHKL
CLK
V
IH
V
IL
tSP
tHD
A[21:0]
V
IH
V
IL
V
IH
V
IL
VALID
ADDRESS
tSP
tHD
ADV#
LB#/UB#
V
IH
V
IL
tCSP
tSP tHD
tHD
tCEM
tCBPH
CE#
V
IH
V
IL
V
IH
V
IL
tSP
tHD
V
IH
V
IL
V
OH
tCEW
High-Z
tSP
V
IH
tKHTL
OE#
WE#
tHZ
High-Z
tHD
WAIT
V
OL
DQ[15:0]
V
IL
WRITE Burst Identified
(WE# = LOW)
D[0]
D[1]
D[2]
D[3]
DON’T CARE
Notes: 1. Non-default BCR settings for burst WRITE operation: Latency code two (three clocks);
WAIT active LOW; WAIT asserted during delay.
2. Clock rates below 50 MHz (
t
CLK > 20ns) are allowed as long as
t
CSP specifications are met.
Table 31:
Burst WRITE Timing Parameters
-708
-706/-856
Min
5
8
7.5
20
20
1
15
5
2
8
7.5
20
20
Max
Units
ns
µs
ns
ns
ns
ns
Symbol
t
-708
Min
Max
8
1.8
9
4
3
-706/-856
Min
Max
8
2.0
11
5
3
Units
ns
ns
ns
ns
ns
Symbol
t
Min
5
1
12.5
4.5
2
Max
CBPH
t
CEM
t
CEW
t
CLK
t
CSP
t
HD
HZ
t
KHKL
t
KHTL
t
KP
t
SP
PDF: 09005aef80be1fbd/Source: 09005aef80be2036
Burst CellularRAM_2.fm - Rev. G 10/05 EN
50
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©2003 Micron Technology, Inc. All rights reserved.
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