Advanced v1.1
Core1553BRT-EBR Enhanced Bit Rate 1553
Remote Terminal
Product Summary
Intended Use
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•
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1553 Enhanced Bit Rate Remote Terminal (RT)
DMA Backend Interface to External Memory
Direct Backend Interface to Devices
Space and Avionic Applications
Development System
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Complete 1553BRT-EBR Implementation, Implemented
in an AX1000
Synthesis and Simulation Support
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Synthesis: Exemplar
™
, Synplicity
®
, Design Compiler
®
,
FPGA Compiler
™
Simulation: Vital-Compliant VHDL Simulators and
OVI-Compliant Verilog Simulators
Key Features
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Supports Enhanced Bit Rate 1553
10 Mbps Time-Multiplexed Serial Data Bus
Interfaces to External RAM or Directly to Backend
Device
Synchronous or Asynchronous Backend Interface
Encoders and Decoders Operate off 100 MHz Clock
Protocol Control and Memory Interface Operates
off 50 MHz Clock
Interfaces to Standard RS485 Transceivers
Programmable Mode Code and Sub-Address
Legality for Illegal Command Support
Memory Address Mapping Allowing Emulation of
Legacy Remote Terminals
Fail-Safe State Machines
Fully Synchronous Operation
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Verification and Compliance
Meets Requirements of Draft SAE AS5682 Standard
(2005-10)
Actel-Developed Simulation Testbench Implements
a Subset of the RT Test Plan (MIL-HDBK-1553A) for
Protocol Verification
Protocol Control Derived from Core1553BRT,
which Is Certified to MIL-STD-1553B (RT Validation
Test Plan MIL-HDBK-1553, Appendix A)
Contents
Supported Families
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ProASIC
®
3/E
ProASIC
PLUS®
Axcelerator
®
RTAX-S
Core Deliverables
•
Netlist Version
–
–
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Compiled RTL Simulation Model, Compliant with
Actel Libero
®
Integrated Design Environment (IDE)
Netlist Compatible with the Actel Designer
Place-and-Route Tool (with and without I/O Pads)
VHDL or Verilog Core Source Code
Synthesis Scripts
RTL Version
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Actel-Developed Testbench (VHDL)
February 2006
© 2006 Actel Corporation
A d v an c ed v 1 .1
1
ACTEL [ Actel Corporation ]
