XIO2221ZAY 参数 Datasheet PDF下载

SCPS216A – JULY 2009 – REVISED FEBRAURY 2010

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8.22 Interrupt Mask Register

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8.23 Isochronous Transmit Interrupt Event Register

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8.24 Isochronous Transmit Interrupt Mask Register

......................................................................

8.25 Isochronous Receive Interrupt Event Register

.......................................................................

8.26 Isochronous Receive Interrupt Mask Register

.......................................................................

8.27 Initial Bandwidth Available Register

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8.28 Initial Channels Available High Register

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8.29 Initial Channels Available Low Register

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8.30 Fairness Control Register

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8.31 Link Control Register

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8.32 Node Identification Register

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8.33 PHY Control Register

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8.34 Isochronous Cycle Timer Register

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8.35 Asynchronous Request Filter High Register

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8.36 Asynchronous Request Filter Low Register

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8.37 Physical Request Filter High Register

.................................................................................

8.38 Physical Request Filter Low Register

.................................................................................

8.39 Physical Upper Bound Register (Optional Register)

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8.40 Asynchronous Context Control Register

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8.41 Asynchronous Context Command Pointer Register

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8.42 Isochronous Transmit Context Control Register

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8.43 Isochronous Transmit Context Command Pointer Register

........................................................

8.44 Isochronous Receive Context Control Register

......................................................................

8.45 Isochronous Receive Context Command Pointer Register

.........................................................

8.46 Isochronous Receive Context Match Register

.......................................................................

1394 OHCI Memory-Mapped TI Extension Register Space

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9.1

Digital Video (DV) and MPEG2 Timestamp Enhancements

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9.2

Isochronous Receive Digital Video Enhancements

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9.3

Isochronous Receive Digital Video Enhancement Registers

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9.4

Link Enhancement Control Registers

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9.5

Timestamp Offset Registers

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Physical Layer (PHY) Section

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10.1 PHY Section Register Configuration

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10.2 PHY Section Application Information

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10.2.1 Power Class Programming

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10.2.2 Power-Up Reset

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10.2.3 Crystal Oscillator Selection

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10.2.4 Bus Reset

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Electrical Characteristics

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11.1 Absolute Maximum Ratings

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11.2 Recommended Operating Conditions

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11.3 PCIe Differential Transmitter Output Ranges

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11.4 PCIe Differential Receiver Input Ranges

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11.5 PCIe Differential Reference Clock Input Ranges

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11.6 Electrical Characteristics Over Recommended Operating Conditions (3.3-V I/O)

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8.21

Interrupt Event Register

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